Patents by Inventor Robert H. Havemann

Robert H. Havemann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4635344
    Abstract: A low temperature, low encroachment isolation technique using differential oxidation results in an isolated semiconductor body having an N+ substrate (12) and an N epi layer (14) forming a mesa. N+ implants (22a) and (22b) are implanted on opposite sides of the mesa. Oxide is grown over the surface of the device with differential oxidation thus resulting in thick regions (24) over the N+ dopant regions and a thin region (26) over the undopant mesa region.
    Type: Grant
    Filed: August 20, 1984
    Date of Patent: January 13, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Robert H. Havemann
  • Patent number: 4621411
    Abstract: Optical illumination rather than furnace heating is used to drive in MOSFET source and drain diffusions, preferably using a surface layer of antimony as the dopant source. This results in substantially less overlap between the gate and the source and drain diffusions. Similarly, if the present invention is practiced in a process having gate sidewalls less than zero overlap can be achieved.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: November 11, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Havemann, Vernon R. Porter
  • Patent number: 4619036
    Abstract: After the extrinsic base region of a bipolar transistor has been formed, and the emitter contact has been patterned and cut, the emitter dopant is deposited or spun on, and the emitter dopant is then driven in using a short pulse of radiant energy. The necessity for high-temperature annealing of the emitter doping is thereby avoided, and the base doping profile is not disturbed by high-temperature annealing steps.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: October 28, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Havemann, Samuel C. Baber
  • Patent number: 4599247
    Abstract: The disclosure relates to a method of growing thermal oxide on silicon wherein the oxide is grown at an increased rate, at reduced temperature or a combination thereof. This is accomplished by operating in an hermetic quartz tube capable of withstanding high pressure with steam or oxygen at super atmospheric pressure.
    Type: Grant
    Filed: January 4, 1985
    Date of Patent: July 8, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth E. Bean, Robert H. Havemann, Andrew Lane
  • Patent number: 4597164
    Abstract: Isolation trenches are formed around selected areas on an integrated circuit device, and highly doped areas are formed in the epitaxial silicon surrounding such trenches. The device is then oxidized at a low temperature, and differential oxidation growth of the highly doped areas causes a thick field oxide to grow outside the trenches while only a thin oxide grows over the selected areas.
    Type: Grant
    Filed: August 31, 1984
    Date of Patent: July 1, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Robert H. Havemann
  • Patent number: 4541167
    Abstract: The disclosure relates to a method manufacturing semiconductor devices which minimizes encroachment by utilizing a polycrystalline silicon (polysilicon) layer over a grown oxide on the substrate with a nitride layer positioned above the polysilicon layer. A patterned resist is then formed in the active device regions and the device is then etched in the regions where the resist has not been applied to remove the nitride layer, the polysilicon layer and the oxide layer in one embodiment and, in a second embodiment, also removes a portion of the substrate. The silicon substrate portion which is exposed is then oxidized by field oxidation to provide, in the first embodiment, an oxide layer which rises above the level of the polysilicon layer and, in the second embodiment, to a point equal to or slightly above the oxide layer beneath the polysilicon layer. The nitride and polysilicon layer are then stripped or, alternatively, the polysilicon layer can be oxidized.
    Type: Grant
    Filed: January 12, 1984
    Date of Patent: September 17, 1985
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Havemann, Gordon P. Pollack