Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Abstract: Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: The present disclosure relates to patient support systems, such as hospital beds, and particularly to reconfigurable patient support systems movable among a number of different positions. The present disclosure further relates to control algorithms and interfaces for use in patient support systems.

Abstract: A vehicle includes a vehicle body including a truck bed at least partially defining a cargo area, a vehicle interior with passenger seating, and a multi-component hard top assembly configured to selectively and removably couple to the vehicle body to provide an enclosed configuration at least partially enclosing the vehicle interior. The multi-component hard top assembly includes a rear window assembly configured to selectively and removably couple to the vehicle body.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: The invention is a modular card processing and attaching system configured to provide uninterrupted workflow in the feeding and subsequent attaching of cards to carriers for the formation of a mailpiece. The modular card processing and attaching system is further configured to be incorporated into a production mail inserter system, such that attached card and carrier mailpieces may be subsequently sorted and/or inserted into a mailable envelope or packages to be mailed.

Abstract: A temperature sensor for monitoring an organ or tissue is configured to measure a temperature inside of a container configured to contain the organ or tissue. The temperature sensor is disposed exterior to the organ container and the temperature sensor is a non-contact temperature sensor. The temperature sensor may be part of an apparatus for perfusing, transporting, and/or storing an organ or tissue. A coolant container may have an aperture through which the temperature sensor measures a temperature of at least one of the organ or tissue or a perfusate fluid surrounding the organ or tissue. The temperature sensor is preferably an infrared temperature sensor. Multiple temperature sensors may be provided that measure the temperature organ or tissue or perfusate fluid surrounding the organ or tissue, for example in case one of the temperature sensors fails.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Aspects include creating a knowledge base that identifies experts in a set of domains. Front-end processing is provided to an issue tracking system. The front-end processing includes receiving a report of an issue related to one of the domains, and accessing the knowledge base to locate an expert in the domain. The front-end processing also includes instructing the issue tracking system to route the received report of the issue to the located expert in the domain. The issue tracking system executes on a different processor than the front-end processing. Data collected from operation of the issue tracking system is monitored, and the knowledge base is updated based at least in part on the data collected from the operation of the issue tracking system.