Abstract: As an example, a walker includes a first leg pair, a second leg pair and a cross beam connecting the first and second leg pairs in a parallel, spaced apart relationship. Each leg pair includes a U-shaped tube defining a front leg and a rear leg. A front strut is telescopically movable within the front leg and extends outwardly therefrom. A rear strut is telescopically movable within the rear leg and extends outwardly therefrom. A mechanical linear actuator includes a rotating element adapted to rotate relative to at least one of the front leg or the rear leg. The rotating element includes an interface with a track on the respective strut relative to which the rotating element rotates, whereby rotational motion of the rotating element translates to corresponding linear motion of the strut.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: The invention is a modular card processing and attaching system configured to provide uninterrupted workflow in the feeding and subsequent attaching of cards to carriers for the formation of a mailpiece. The modular card processing and attaching system is further configured to be incorporated into a production mail inserter system, such that attached card and carrier mailpieces may be subsequently sorted and/or inserted into a mailable envelope or packages to be mailed.

Abstract: A temperature sensor for monitoring an organ or tissue is configured to measure a temperature inside of a container configured to contain the organ or tissue. The temperature sensor is disposed exterior to the organ container and the temperature sensor is a non-contact temperature sensor. The temperature sensor may be part of an apparatus for perfusing, transporting, and/or storing an organ or tissue. A coolant container may have an aperture through which the temperature sensor measures a temperature of at least one of the organ or tissue or a perfusate fluid surrounding the organ or tissue. The temperature sensor is preferably an infrared temperature sensor. Multiple temperature sensors may be provided that measure the temperature organ or tissue or perfusate fluid surrounding the organ or tissue, for example in case one of the temperature sensors fails.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: Folder systems and related methods are provided for accurately and efficiently folding a paper carrier that has a card attached without bending or dislodging the card from the carrier. A movable fold chute receives a portion of the carrier with the card attached and allows the carrier to fold while protecting the card portion of the carrier. The fold chute moves between different positions which allow the carrier to enter and exit through folding rollers along a generally straight paper path without forcing the cards around small radii, thereby preventing damage to the cards or causing them to separate from the carrier sheet.

Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Aspects include creating a knowledge base that identifies experts in a set of domains. Front-end processing is provided to an issue tracking system. The front-end processing includes receiving a report of an issue related to one of the domains, and accessing the knowledge base to locate an expert in the domain. The front-end processing also includes instructing the issue tracking system to route the received report of the issue to the located expert in the domain. The issue tracking system executes on a different processor than the front-end processing. Data collected from operation of the issue tracking system is monitored, and the knowledge base is updated based at least in part on the data collected from the operation of the issue tracking system.

Abstract: A collation folding device comprising one or more fold rollers mounted in fixed positions. Below and adjacent to the fold rollers are adjustable nip rollers to form nip spacing between the rollers. The adjustable nip roller is mounted on a nip axis shaft. An adjustment mechanism is used for moving the nip axis shaft to adjust the nip spacing. The nip adjustment mechanism includes a bearing block cam follower on which the nip axis shaft is fixedly mounted and supported. An eccentric cam in operative contact with the bearing block cam follower. Rotation of the eccentric cam on the eccentric cam axis drives the bearing block cam follower in its linear motion to adjust the nip spacing.

Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: An apparatus for at least one of storage, treatment, assessment and transport of an organ or tissue includes a cooling container configured to cool the organ or tissue, a perfusion circuit configured to perfuse the organ or tissue, and a sample compartment for holding a biological sample. Preferred apparatus has a first internal compartment under a first cover (lid) of the apparatus that includes the coolant container and the sample compartment. The apparatus can include a second internal compartment under a second cover (lid) of the apparatus, the second internal compartment including at least part of the perfusion circuit and a sample compartment.