Patents by Inventor Robert J. Allen

Robert J. Allen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11027242
    Abstract: The present invention provides nanofiltration membranes with reduced chemical reactivity that can be utilized in manufacturing processes where reactive feedstocks and/or products are utilized or produced. Methods of making and using the membranes are also provided.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 8, 2021
    Assignee: Novomer, Inc.
    Inventors: Robert E. Lapointe, Scott D. Allen, Han Lee, Thomas Widzinski, Jay J. Farmer
  • Patent number: 11008580
    Abstract: This invention provides molecular constructs and methods for the temporally specific control of gene expression in plants or in plant pests or pathogens. More specifically, this invention provides plant miRNA genes having novel circadian expression patterns that are useful for designing recombinant DNA constructs for temporally specific expression of at least one gene. Also provided are non-natural transgenic plant cells, plants, and seeds containing in their genome a recombinant DNA construct of this invention.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: May 18, 2021
    Assignee: MONSANTO TECHNOLOGY LLC
    Inventors: Edwards M. Allen, Sara E. Heisel, Sergey Ivashuta, Elysia K. Krieger, Jennifer Lutke, Robert J. Meister, Yuanji Zhang
  • Publication number: 20210113416
    Abstract: As an example, a walker includes a first leg pair, a second leg pair and a cross beam connecting the first and second leg pairs in a parallel, spaced apart relationship. Each leg pair includes a U-shaped tube defining a front leg and a rear leg. A front strut is telescopically movable within the front leg and extends outwardly therefrom. A rear strut is telescopically movable within the rear leg and extends outwardly therefrom. A mechanical linear actuator includes a rotating element adapted to rotate relative to at least one of the front leg or the rear leg. The rotating element includes an interface with a track on the respective strut relative to which the rotating element rotates, whereby rotational motion of the rotating element translates to corresponding linear motion of the strut.
    Type: Application
    Filed: August 14, 2020
    Publication date: April 22, 2021
    Inventors: Ronald J. Triolo, Marc Louis Vitantonio, Robert Craig Allen, Shawn William Dellinger, Anna E. Krakora
  • Publication number: 20210116214
    Abstract: Switchless sensing is provided to control electronic devices of the type associated with deterrent devices.
    Type: Application
    Filed: March 13, 2020
    Publication date: April 22, 2021
    Inventors: Jeffrey W. Mock, John A. Kowalczyk, JR., Eric St. Phillips, Christopher A. Gagliano, Michael W. Allen, Robert J. MacBlane
  • Patent number: 10949593
    Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao
  • Publication number: 20190332735
    Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.
    Type: Application
    Filed: July 12, 2019
    Publication date: October 31, 2019
    Inventors: Robert J. ALLEN, Yanai DANAN, Vasant RAO, Jeffrey P. SOREFF, Xin ZHAO
  • Patent number: 10394986
    Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao
  • Patent number: 10380286
    Abstract: The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Debjit Sinha, Natesan Venkateswaran, Vladimir Zolotov
  • Patent number: 10380289
    Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Debjit Sinha, Natesan Venkateswaran, Vladimir Zolotov
  • Patent number: 10360329
    Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert J. Allen, Vasant B. Rao, William J. Wright, Xin Zhao
  • Patent number: 10354041
    Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert J. Allen, Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny, Ronald D. Rose, David J. Widiger
  • Patent number: 10346569
    Abstract: Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Debjit Sinha, Natesan Venkateswaran, Vladimir Zolotov
  • Publication number: 20190138916
    Abstract: Aspects include creating a knowledge base that identifies experts in a set of domains. Front-end processing is provided to an issue tracking system. The front-end processing includes receiving a report of an issue related to one of the domains, and accessing the knowledge base to locate an expert in the domain. The front-end processing also includes instructing the issue tracking system to route the received report of the issue to the located expert in the domain. The issue tracking system executes on a different processor than the front-end processing. Data collected from operation of the issue tracking system is monitored, and the knowledge base is updated based at least in part on the data collected from the operation of the issue tracking system.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Robert J. Allen, Adil Bhanji, Vasant B. Rao, Peter A. Twombly, Loma D. Vaishnav, Xin Zhao
  • Patent number: 10196228
    Abstract: A collation folding device comprising one or more fold rollers mounted in fixed positions. Below and adjacent to the fold rollers are adjustable nip rollers to form nip spacing between the rollers. The adjustable nip roller is mounted on a nip axis shaft. An adjustment mechanism is used for moving the nip axis shaft to adjust the nip spacing. The nip adjustment mechanism includes a bearing block cam follower on which the nip axis shaft is fixedly mounted and supported. An eccentric cam in operative contact with the bearing block cam follower. Rotation of the eccentric cam on the eccentric cam axis drives the bearing block cam follower in its linear motion to adjust the nip spacing.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: February 5, 2019
    Assignee: DMT Solutions Global Corporation
    Inventors: Robert J Allen, Michael R Ifkovits, Boris Rozenfeld, George Cruz, Edward M. Ifkovits
  • Publication number: 20180373830
    Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.
    Type: Application
    Filed: May 25, 2018
    Publication date: December 27, 2018
    Inventors: Robert J. ALLEN, Yanai DANAN, Vasant RAO, Jeffrey P. SOREFF, Xin ZHAO
  • Patent number: 10091987
    Abstract: An apparatus for at least one of storage, treatment, assessment and transport of an organ or tissue includes a cooling container configured to cool the organ or tissue, a perfusion circuit configured to perfuse the organ or tissue, and a sample compartment for holding a biological sample. Preferred apparatus has a first internal compartment under a first cover (lid) of the apparatus that includes the coolant container and the sample compartment. The apparatus can include a second internal compartment under a second cover (lid) of the apparatus, the second internal compartment including at least part of the perfusion circuit and a sample compartment.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 9, 2018
    Assignee: LIFELINE SCIENTIFIC, INC.
    Inventors: David Kravitz, Christopher P. Steinman, David Pettinato, Matthew Copithorne, Brian Otts, Robert J. Allen, Frank P. Nanna, Peter Demuylder
  • Publication number: 20180239860
    Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.
    Type: Application
    Filed: December 22, 2017
    Publication date: August 23, 2018
    Inventors: Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Debjit Sinha, Natesan Venkateswaran, Vladimir Zolotov
  • Publication number: 20180239859
    Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.
    Type: Application
    Filed: November 27, 2017
    Publication date: August 23, 2018
    Inventors: Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Debjit Sinha, Natesan Venkateswaran, Vladimir Zolotov
  • Publication number: 20180239858
    Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.
    Type: Application
    Filed: February 20, 2017
    Publication date: August 23, 2018
    Inventors: Robert J. Allen, Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Debjit Sinha, Natesan Venkateswaran, Vladimir Zolotov
  • Patent number: 10031988
    Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert J. Allen, Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao