Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: An apparatus for at least one of storage, treatment, assessment and transport of an organ or tissue includes a cooling container configured to cool the organ or tissue, a perfusion circuit configured to perfuse the organ or tissue, and a sample compartment for holding a biological sample. Preferred apparatus has a first internal compartment under a first cover (lid) of the apparatus that includes the coolant container and the sample compartment. The apparatus can include a second internal compartment under a second cover (lid) of the apparatus, the second internal compartment including at least part of the perfusion circuit and a sample compartment.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Abstract: An apparatus for at least one of storage, treatment, assessment and transport of an organ or tissue includes a cooling container configured to cool the organ or tissue, a perfusion circuit configured to perfuse the organ or tissue, and a sample compartment for holding a biological sample. Preferred apparatus has a first internal compartment under a first cover (lid) of the apparatus that includes the coolant container and the sample compartment. The apparatus can include a second internal compartment under a second cover (lid) of the apparatus, the second internal compartment including at least part of the perfusion circuit and a sample compartment.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: A collation folding device comprising one or more fold rollers mounted in fixed positions. Below and adjacent to the fold rollers are adjustable nip rollers to form nip spacing between the rollers. The adjustable nip roller is mounted on a nip axis shaft. An adjustment mechanism is used for moving the nip axis shaft to adjust the nip spacing. The nip adjustment mechanism includes a bearing block cam follower on which the nip axis shaft is fixedly mounted and supported. An eccentric cam in operative contact with the bearing block cam follower. Rotation of the eccentric cam on the eccentric cam axis drives the bearing block cam follower in its linear motion to adjust the nip spacing.

Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.

Abstract: One or more processors group a plurality of timing arcs into a plurality of equivalence classes. Each timing arc includes one or more delay tables. One or more processors generate, for at least one equivalence class of the plurality of equivalence classes, an average sensitivity to a condition by performing a weighted average on respective sensitivities of timing arcs to the condition. One or more processors determine a sensitivity of an electronic circuit to the condition based, at least in part, a match between one or more attributes of the electronic circuit and one or more attributes present in the at least one equivalence class.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.

Abstract: Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.

Abstract: An apparatus for at least one of storage, treatment, assessment and transport of an organ or tissue includes a cooling container configured to cool the organ or tissue, a perfusion circuit configured to perfuse the organ or tissue, and a sample compartment for holding a biological sample. Preferred apparatus has a first internal compartment under a first cover (lid) of the apparatus that includes the coolant container and the sample compartment. The apparatus can include a second internal compartment under a second cover (lid) of the apparatus, the second internal compartment including at least part of the perfusion circuit and a sample compartment.

Abstract: Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.

Abstract: An apparatus for at least one of storage, treatment, assessment and transport of an organ or tissue includes a cooling container configured to cool the organ or tissue, a perfusion circuit configured to perfuse the organ or tissue, and a sample compartment for holding a biological sample. Preferred apparatus has a first internal compartment under a first cover (lid) of the apparatus that includes the coolant container and the sample compartment. The apparatus can include a second internal compartment under a second cover (lid) of the apparatus, the second internal compartment including at least part of the perfusion circuit and a sample compartment.

Abstract: An apparatus for at least one of storage, treatment, assessment and transport of an organ or tissue includes a coolant container configured to cool the organ or tissue, a perfusion circuit configured to perfuse the organ or tissue, and a sample compartment for holding a biological sample. Preferred apparatus has a first internal compartment under a first cover (lid) of the apparatus that includes the coolant container and the sample compartment. The apparatus can include a second internal compartment under a second cover (lid) of the apparatus, the second internal compartment including at least part of the perfusion circuit and a sample compartment.

Abstract: A perfusion apparatus including a perfusion circuit that perfuses an organ or tissue has a compartment that supports an organ or tissue during perfusion, an internal cover, and an external cover that closes the apparatus. A wall portion may extend substantially perpendicularly between the internal cover and the external cover to define a document compartment between the internal cover, the external cover and the wall portion. A tamper evident seal will not permit the external cover to open without creating a record of whether the external cover has been opened after the tamper evident seal has been activated.