Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.

Abstract: A clamping circuit which is connected to each long line, preferably adjacent the receiver. The clamping circuit biases the long line at the trigger threshold of the receiver. Thus, instead of amplifying the signal as a repeater will do, the present invention clamps the line to the threshold, thus allowing a faster response since the line doesn't have to be charged or discharged from a lower or higher level to the threshold. This thus speeds up the transition at the receiver without requiring a repeater or a keeper.

Abstract: An improved signal buffer configuration has been developed for transmitting communication signals across line traces between ICs on a printed circuit board, printed wiring board, multi-chip module, integrated circuit carrier or package, or other interconnect substrate. For example, in some realizations, multiple ICs having mismatched input and output impedances are mounted on an printed circuit board and communicate with each other via line traces. A signal buffer IC is placed in-line with the connecting line trace. The buffer is sized to fit within the pitch spacing of the line trace and contains an input impedance control circuit and an output impedance control circuit. These impedance control circuits are adapted to receive a control signal to set the input and output impedances of the buffer to correspond to the impedances of the connecting line traces. In this manner, the impedances between the ICs connected by this line trace are effectively matched and transmission line errors between them are reduced.

Abstract: A bi-directional communication system and transceiver configuration are described, which employ a bidirectional reference to account for both common-mode and differential noise introduced at either end of a bidirectional communication channel. Some implementations exploit the techniques described in a bi-directional chip-to-chip communication scheme. In some implementations, the advantages of bi-directional reference techniques described herein are obtained while pre-distortion of transmitted signals is employed to compensate for intersymbol interference (ISI) in a communications channel.

Abstract: An improved signal buffer configuration has been developed for transmitting communication signals across line traces between ICs on a printed circuit board, printed wiring board, multi-chip module, integrated circuit carrier or package, or other interconnect substrate. For example, in some realizations, multiple ICs having mismatched input and output impedances are mounted on an printed circuit board and communicate with each other via line traces. A signal buffer IC is placed in-line with the connecting line trace. The buffer is sized to fit within the pitch spacing of the line trace and contains an input impedance control circuit and an output impedance control circuit. These impedance control circuits are adapted to receive a control signal to set the input and output impedances of the buffer to correspond to the impedances of the connecting line traces. In this manner, the impedances between the ICs connected by this line trace are effectively matched and transmission line errors between them are reduced.

Abstract: A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.

Abstract: One embodiment of the present invention provides a system for capacitively probing electrical signals within an integrated circuit. This system operates by placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit. In this position, the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor. Next, the system detects a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor, and then determines a logic value for the target conductor based on the change in the probe voltage. In one embodiment of the present invention, determining the logic value for the target conductor involves, determining a first value if the probe voltage decreases, and determining a second value if the probe voltage increases.

Abstract: A low-pass filter to filter the internal bias voltages. It is connected locally at the bias voltage input of each bias current source the low-pass filter reduces the AC overshoot oscillations of a local bias voltage generated by the bias voltage generator upon a changing in the amount of current sourced by other current sources. A single bias voltage generator is connected to a bias voltage input of a number of bias current sources. Each current source has a low pass filter to filter the bias voltage.

Abstract: A sense amplifier having dual differential inputs configured to accept differential analog input voltages. The differential analog input voltages are fused to determine a weighted signal digitally representative of the differential analog input voltages. An input offset voltage cancellation circuit may be coupled to the sense amplifier to reduce an input offset voltage of the sense amplifier.

Abstract: A clock buffer circuit utilizing an LC circuit for jitter reduction. The circuit includes a differential amplifier that is coupled to a buffer stage. The output of the buffer circuit comprises the buffer stage output. An inductor and capacitor are coupled between the buffer stage output and ground. The values of the inductor and capacitor are specified such that the resonant frequency of the LC circuit corresponds to the nominal clock frequency. The entire buffer circuit including the capacitor and inductor may be fabricated on an integrated circuit. Alternatively the capacitor and/or inductor may comprise discrete components that are coupled to the buffer stage output. Additionally, multiple capacitors and/or inductors may be fabricated on the integrated circuit to permit the resonant frequency of the LC circuit to be adjusted to match the nominal clock frequency.

Abstract: In an input receiver circuit includes a signal input for receiving a signal input to a chip, a chip output for supplying a buffered signal to circuitry on the chip and a positive feedback circuit coupled between the chip output and the signal input. The positive feedback circuit might comprise a first inverter having an input coupled to the signal input, a second inverter having an input coupled to an output of the first inverter, wherein an output of the second inverter provides the chip output, and an inverting buffer having an input coupled to the output of the second inverter and an output coupled to the signal input.

Abstract: An improved loop filter contains an active device which maintains a phase lock loop's zero frequency to bandwidth ratio substantially constant with changes in the incoming frequency. It does this by maintaining filter resistance proportional to the inverse square root of the filter current, and without requiring duplicates of circuit elements. Constructed in this way a phase lock loop can be achieved which has a wide operating frequency range and low tracking jitter.

Abstract: An improved output driver for HSTL includes a bias control transistor to absorb current leaking through the base-collector capacitance of the drive transistor and maintain the base voltage on the drive transistor. The bias control transistor is biased by a series network coupled between a base of the bias control transistor and ground, which keeps the bias control transistor at a bias near its turn-on bias, with a feedback capacitor coupled between the output and the base of the bias control transistor to turn on the bias control transistor when the output rises.

Abstract: A high speed self-terminated output driver includes an array of resistive drivers that are pulse-activated in succession to process a corresponding succession of data bits. The output driver thus synthesizes an output waveform which behaves similar to a single resistive drive element responding to the non-bandlimited input signal. In various embodiment, the output driver provides for digitally programmable output impedance and pre-distortion levels.

Abstract: A CMOS impedance matching circuit includes an amplifier and a feedback circuit. The amplifier allows control of the impedance by controlling the V/I characteristic. The amplifier is sized to provide the desired impedance. The feedback circuit clamps the maximum excursions of the input signal, thereby maximizing signal speed. It also provides a higher impedance to noise beyond the dead band. In one embodiment of the present invention, the amplifier includes an amplifier circuit in parallel with an amplifier buffer. The amplifier buffer provides no gain and simply performs the inverting function when no gain is required for impedance matching. In one embodiment, the amplifier circuit includes a plurality of switchable amplifiers coupled in parallel with each other. Each of the switchable amplifiers has a different gain, and the one with the right amount of gain for the needed impedance matching is chosen using control inputs.

Abstract: A delay-locked loop includes a phase detection circuit, a charge pump circuit and a phase shift circuit. The phase detection circuit is coupled to receive a first signal and a second signal. The phase detection circuit generates a phase-error output signal indicative of whether the first signal is ahead of or behind the second signal in phase responsive to receiving the first and second signals. The charge pump circuit is coupled to receive a phase-error signal derived from the phase-error output signal. The charge pump circuit generates a plurality of control output signals. Each of the control output signals are based upon the phase-error signal and by at least one signal derived from one other of the control output signals. The phase shift circuit is coupled to receive a plurality of control input signals and a plurality of periodic input signals. The control input signals are derived from the control output signals. Each of the periodic input signals have a different phase.

Abstract: A decoder circuit for decoding phase-encoded digital data signals includes a timing circuit and a signal viewer circuit coupled to logic circuitry. The timing circuit uses an edge of a received phase-encoded digital data signal to indicate when to sample data from the received phase-encoded digital data signal in the signal viewer circuit. The logic circuitry determines the value encoded in the phase-encoded digital data signal based on the sampled data.

Abstract: An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal.

Abstract: A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a timing parameter of a transmit clock, resulting in an increase in a bit error rate of the chip. Artificially increasing the bit error rate of the chip reduces the amount of time required to test the chip to determine the acceptability of the chip and its actual bit error rate.

Abstract: An apparatus for suppressing the effect of noise from a first circuit on the performance of a second circuit wherein the first and second circuits are on a common substrate. Each of the first and second circuits include first and second supply rails. The apparatus includes a noise isolation circuit and a noise transference circuit. The noise isolation circuit is for coupling the first supply rails of the first and second circuits to prevent noise on the first supply rail of the first circuit from transferring to the first supply rail of the second circuit. The noise transference circuit is for coupling the second supply rails of the first and second circuits so that noise on the second supply rail of the first circuit is transferred to the second supply rail of the second circuit.