Patents by Inventor Robert J. Contolini

Robert J. Contolini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7070686
    Abstract: In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: July 4, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Robert J. Contolini, Andrew J. McCutcheon, Steven T. Mayer
  • Patent number: 6716334
    Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: April 6, 2004
    Assignee: Novellus Systems, Inc
    Inventors: Jonathan D. Reid, Steven W. Taatjes, Robert J. Contolini, Evan E. Patton
  • Patent number: 6709565
    Abstract: The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: March 23, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Robert J. Contolini, Eliot K. Broadbent, John S. Drewery
  • Patent number: 6569299
    Abstract: An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: May 27, 2003
    Assignees: Novellus Systems, Inc., International Business Machines, Corp.
    Inventors: Jonathan David Reid, Robert J. Contolini, John Owen Dukovic
  • Publication number: 20030079995
    Abstract: In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.
    Type: Application
    Filed: October 21, 2002
    Publication date: May 1, 2003
    Applicant: Novellus Systems, Inc.
    Inventors: Robert J. Contolini, Andrew J. McCutcheon, Steven T. Mayer
  • Patent number: 6514393
    Abstract: An electrochemical reactor is used to electrofill damascene architecture for integrated circuits or for electropolishing magnetic disks. An inflatable bladder is used to screen the applied field during electroplating operations to compensate for potential drop along the radius of a wafer. The bladder establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film seed layer of copper on the wafer.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: February 4, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Robert J. Contolini, Andrew J. McCutcheon
  • Publication number: 20020074238
    Abstract: The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.
    Type: Application
    Filed: September 28, 2001
    Publication date: June 20, 2002
    Inventors: Steven T. Mayer, Robert J. Contolini, Eliot K. Broadbent, John S. Drewery
  • Patent number: 6315883
    Abstract: A disclosed electroplanarization process involves “masking” certain regions of a wafer surface during electropolishing. The regions chosen for masking are features of relatively low aspect ratio (i.e., features that are wider than they are deep). The masking is accomplished with a material of relatively low ionic conductivity, which effectively slows or blocks transport of the metal ions produced during electropolishing. Examples of masking materials include concentrated phosphoric acid and certain polymers.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: November 13, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Robert J. Contolini
  • Patent number: 6261961
    Abstract: A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO2), silicon nitride (SiNx), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: July 17, 2001
    Assignee: The Regents of the University of California
    Inventors: Jeffrey D. Morse, Robert J. Contolini
  • Patent number: 6214193
    Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: April 10, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Steven W. Taatjes, Robert J. Contolini, Evan E. Patton
  • Patent number: 6193870
    Abstract: A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: February 27, 2001
    Assignee: The Regents of the University of California
    Inventors: Jeffrey D. Morse, Robert J. Contolini
  • Patent number: 6193859
    Abstract: An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: February 27, 2001
    Assignees: Novellus Systems, Inc., International Business Machines Corporation
    Inventors: Robert J. Contolini, Jonathan Reid, Evan Patton, Jingbin Feng, Steve Taatjes, John Owen Dukovic
  • Patent number: 6162344
    Abstract: In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: December 19, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Robert J. Contolini, Edward C. Opocensky, Evan E. Patton, Eliot K. Broadbent
  • Patent number: 6159354
    Abstract: An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: December 12, 2000
    Assignees: Novellus Systems, Inc., International Business Machines, Inc.
    Inventors: Robert J. Contolini, Jonathan Reid, Evan Patton, Jingbin Feng, Steve Taatjes, John Owen Dukovic
  • Patent number: 6139716
    Abstract: A wet chemical process for etching submicron patterned holes in thin metal layers using electrochemical etching with the aid of a wetting agent. In this process, the processed wafer to be etched is immersed in a wetting agent, such as methanol, for a few seconds prior to inserting the processed wafer into an electrochemical etching setup, with the wafer maintained horizontal during transfer to maintain a film of methanol covering the patterned areas. The electrochemical etching setup includes a tube which seals the edges of the wafer preventing loss of the methanol. An electrolyte composed of 4:1 water: sulfuric is poured into the tube and the electrolyte replaces the wetting agent in the patterned holes. A working electrode is attached to a metal layer of the wafer, with reference and counter electrodes inserted in the electrolyte with all electrodes connected to a potentiostat. A single pulse on the counter electrode, such as a 100 ms pulse at +10.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: October 31, 2000
    Assignee: The Regents of the University of California
    Inventors: Anthony M. McCarthy, Robert J. Contolini, Vladimir Liberman, Jeffrey Morse
  • Patent number: 6126798
    Abstract: An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: October 3, 2000
    Assignees: Novellus Systems, Inc., International Business Machines Corp.
    Inventors: Jonathan David Reid, Robert J. Contolini, John Owen Dukovic
  • Patent number: 6110346
    Abstract: In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: August 29, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Robert J. Contolini, Edward C. Opocensky, Evan E. Patton, Eliot K. Broadbent
  • Patent number: 6099702
    Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: August 8, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Steven W. Taatjes, Robert J. Contolini, Evan E. Patton
  • Patent number: 6074544
    Abstract: In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: June 13, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Robert J. Contolini, Edward C. Opocensky, Evan E. Patton, Eliot K. Broadbent
  • Patent number: 6051493
    Abstract: A method which protects the region between a component and the substrate onto which the components is bonded using an electrically insulating fillet of photoresist. The fillet protects the regions from subsequent plating with metal and therefore shorting the plated conductors which run down the sides of the component and onto the substrate.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: April 18, 2000
    Assignee: The Regents of the University of California
    Inventors: Lisa A. Tarte, Wayne L. Bonde, Paul G. Carey, Robert J. Contolini, Anthony M. McCarthy