Abstract: A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Abstract: A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant.

Abstract: Spacers for applications such as field emission flat panel displays and vacuum microelectronics, and which involves the application of aerogel/xerogel technology to the formation of the spacer. In a preferred approach the method uses a mold and mold release agent wherein the gel precursor is a liquid which can be applied to the mold filling holes which expose the substrate (either the baseplate or the faceplate). A release agent is applied to the mold prior to precursor application to ease removal of the mold after formation of the dielectric spacer. The shrinkage of the gel during solvent extraction also improves mold removal. The final spacer material is a good dielectric, such as silica, secured to the substrate.

Abstract: A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets.For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Abstract: A process of removing both the field metal, such as copper, and a metal, such as copper, embedded into a dielectric or substrate at substantially the same rate by dripping or spraying a suitable metal etchant onto a spinning wafer to etch the metal evenly on the entire surface of the wafer. By this process the field metal is etched away completely while etching of the metal inside patterned features in the dielectric at the same or a lesser rate. This process is dependent on the type of chemical etchant used, the concentration and the temperature of the solution, and also the rate of spin speed of the wafer during the etching. The process substantially reduces the metal removal time compared to mechanical polishing, for example, and can be carried out using significantly less expensive equipment.

Abstract: In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.

Abstract: The present invention provides a microchannel heat sink with a thermal range from cryogenic temperatures to several hundred degrees centigrade. The heat sink can be used with a variety of fluids, such as cryogenic or corrosive fluids, and can be operated at a high pressure. The heat sink comprises a microchannel layer preferably formed of silicon, and a manifold layer preferably formed of glass. The manifold layer comprises an inlet groove and outlet groove which define an inlet manifold and an outlet manifold. The inlet manifold delivers coolant to the inlet section of the microchannels, and the outlet manifold receives coolant from the outlet section of the microchannels. In one embodiment, the manifold layer comprises an inlet hole extending through the manifold layer to the inlet manifold, and an outlet hole extending through the manifold layer to the outlet manifold. Coolant is supplied to the heat sink through a conduit assembly connected to the heat sink.

Abstract: In an electropolishing or electrolytic etching apparatus the anode is separated from the cathode to prevent bubble transport to the anode and to produce a uniform current distribution at the anode by means of a solid nonconducting anode-cathode barrier. The anode extends into the top of the barrier and the cathode is outside the barrier. A virtual cathode hole formed in the bottom of the barrier below the level of the cathode permits current flow while preventing bubble transport. The anode is rotatable and oriented horizontally facing down. An extended anode is formed by mounting the workpiece in a holder which extends the electropolishing or etching area beyond the edge of the workpiece to reduce edge effects at the workpiece. A reference electrode controls cell voltage. Endpoint detection and current shut-off stop polishing. Spatially uniform polishing or etching can be rapidly performed.