Patents by Inventor Robert J. Falster

Robert J. Falster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11764071
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 19, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 11655560
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 23, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, Hyungmin Lee, Byungchun Kim, Robert J. Falster
  • Patent number: 11655559
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 23, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, HyungMin Lee, ByungChun Kim, Robert J. Falster
  • Patent number: 11282715
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 22, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 11276583
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 15, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 11276582
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 15, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20220056616
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Application
    Filed: September 10, 2021
    Publication date: February 24, 2022
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, HyungMin Lee, ByungChun Kim, Robert J. Falster
  • Publication number: 20210404088
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, HyungMin Lee, ByungChun Kim, Robert J. Falster
  • Patent number: 11142844
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 12, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, HyungMin Lee, ByungChun Kim, Robert J. Falster
  • Publication number: 20200216975
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Application
    Filed: June 6, 2017
    Publication date: July 9, 2020
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, HyungMin Lee, ByungChun Kim, Robert J. Falster
  • Patent number: 10707093
    Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 7, 2020
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Young Jung Lee, Jae-Woo Ryu, Byung Chun Kim, Robert J. Falster, Soon Sung Park, Tae Hoon Kim, Jun Hwan Ji, Carissima Marie Hudson
  • Publication number: 20190333778
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 31, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 10453703
    Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 22, 2019
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Young Jung Lee, Jae-Woo Ryu, Byung Chun Kim, Robert J. Falster, Soon Sung Park, Tae Hoon Kim, Jun Hwan Ji, Carissima Marie Hudson
  • Publication number: 20190311912
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20190311913
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20190295853
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20190267251
    Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Inventors: Young Jung Lee, Jae-Woo Ryu, Byung Chun Kim, Robert J. Falster, Soon Sung Park, Tae Hoon Kim, Jun Hwan Ji, Carissima Marie Hudson
  • Patent number: 10361097
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 23, 2019
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 9634098
    Abstract: A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 25, 2017
    Assignee: SunEdison Semiconductor Ltd. (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov
  • Patent number: 9583364
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 28, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht