Patents by Inventor Robert J. Gauthier

Robert J. Gauthier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit protection during high-current ESD testing
    Patent number: 9435841
    Abstract: A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: September 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, James Paul Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra
  • Series-connected nanowire structures
    Patent number: 9431388
    Abstract: Series-connected nanowire structures and methods of manufacture are disclosed. The structure includes a plurality of vertically stacked nanowires extending through a gate structure. The structure further includes a plurality of conductively doped contacts connecting to the stacked nanowires in a series configuration.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Gauthier, Jr., Terence B. Hook, Souvick Mitra
  • Self-healing electrostatic discharge power clamp
    Patent number: 9425185
    Abstract: Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, and a power clamp device coupled with the timing circuit at the node. The capacitor includes a plurality of capacitor elements. The protection circuit further includes a plurality of electronic fuses. Each electronic fuse is coupled with a respective one of the capacitor elements. A field effect transistor may be coupled in parallel with the resistor of the timing circuit, and may be used to bypass the resistor to provide a programming current to any electronic fuse coupled with a capacitor element of abnormally low impedance.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, You Li, Souvick Mitra
  • Electrostatic discharge protection circuit with a fail-safe mechanism
    Patent number: 9413169
    Abstract: Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: August 9, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Gate-all-around fin device
    Patent number: 9397163
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: July 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • Passive devices for FinFET integrated circuit technologies
    Patent number: 9397086
    Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Robert J. Gauthier, Jr., Junjun Li
  • Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode
    Patent number: 9391065
    Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Gauthier, Jr., Tom C. Lee, You Li, Rahul Mishra, Souvick Mitra, Andreas Scholze
  • HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION
    Publication number: 20160197080
    Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
    Type: Application
    Filed: March 11, 2016
    Publication date: July 7, 2016
    Applicant: GlobalFoundries Inc.
    Inventors: John B. Campi, JR., Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • Cancellation of secondary reverse reflections in a very-fast transmission line pulse system
    Patent number: 9377496
    Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shunhua T. Chang, James P. Di Sarro, Robert J. Gauthier, Jr.
  • ELECTROSTATIC DISCHARGE POWER CLAMP WITH FAIL-SAFE DESIGN
    Publication number: 20160181796
    Abstract: Electrostatic discharge protection circuits and methods of fabricating an electrostatic discharge protection circuit, as well as methods of protecting an integrated circuit from a transient electrostatic discharge event. The electrostatic discharge protection circuit includes a power clamp device, a first timing circuit with a first resistor and a first capacitor that is coupled with the first resistor at a first node, and a second timing circuit including a second resistor and a second capacitor that is coupled with the second resistor at a second node. The electrostatic discharge protection circuit further includes a logic gate with a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device. The logic gate responds to voltages at the first and second nodes to control the impedance state of the power clamp device.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: John A. Fifield, Robert J. Gauthier, JR., Junjun Li
  • GATE-ALL-AROUND FIN DEVICE
    Publication number: 20160181162
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Application
    Filed: October 14, 2015
    Publication date: June 23, 2016
    Inventors: John B. CAMPI, JR., Robert J. GAUTHIER, JR., Rahul MISHRA, Souvick MITRA, Mujahid MUHAMMAD
  • High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region
    Patent number: 9349732
    Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • GATE-ALL-AROUND FIN DEVICE
    Publication number: 20160141421
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 19, 2016
    Inventors: John B. Campi, JR., Robert J. Gauthier, JR., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • GATE-ALL-AROUND FIN DEVICE
    Publication number: 20160141365
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Application
    Filed: October 14, 2015
    Publication date: May 19, 2016
    Inventors: John B. CAMPI, JR., Robert J. GAUTHIER, JR., Rahul MISHRA, Souvick MITRA, Mujahid MUHAMMAD
  • SCR WITH FIN BODY REGIONS FOR ESD PROTECTION
    Publication number: 20160111414
    Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.
    Type: Application
    Filed: December 22, 2015
    Publication date: April 21, 2016
    Inventors: James P. DI SARRO, Robert J. GAUTHIER, Tom C. LEE, Junjun LI, Souvick MITRA, Christopher S. PUTNAM
  • TRANSMISSION LINE PULSE AND VERY FAST TRANSMISSION LINE PULSE REFLECTION CONTROL
    Publication number: 20160097804
    Abstract: An approach for transmission line pulse and very fast transmission line pulse reflection control is provided. The approach includes using a power splitter to split an incident pulse into two identical pulses with one going to a device under test (DUT) through a delivery cable and the other going down an open ended delay cable. The structure of the power splitter, along with having the delivery cable and the open ended delay cable with the same signal propagation time and pulse transmission characteristics enable the canceling of pulse reflections from the DUT.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 7, 2016
    Inventors: Shunhua T. Chang, Robert J. Gauthier, JR., Evan Grund
  • Gate-all-around fin device
    Patent number: 9281379
    Abstract: A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: March 8, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. Campi, Jr., Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad
  • Cancellation of secondary reverse reflections in a very-fast transmission line pulse system
    Patent number: 9274155
    Abstract: An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shunhua T. Chang, James P. Di Sarro, Robert J. Gauthier, Jr.
  • Extremely thin semiconductor-on-insulator (ETSOI) layer
    Patent number: 9263517
    Abstract: Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES. INC.
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Self-protected metal-oxide-semiconductor field-effect transistor
    Patent number: 9263402
    Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li