Abstract: A cold plate compatible with the Open Compute Project Rack specification is disclosed. The cold plate is mounted in a compatible rack with removable trays mounted on support and coupling rails affixed to the underside of the cold plate thus supporting the trays during insertion and operation.

Abstract: A system and an method to provide cooling of electronic components mounted in a tray by means of a cold plate, is disclosed. The system comprises a cold plate that is mounted in a rack with removable trays mounted on rails affixed to the underside of the cold plate. In one embodiment, compatibility with Open Rack specifications developed by the Open Compute Project is disclosed.

Abstract: An electronic system cooling apparatus including a cold plate coupled vertically within an enclosure, the cold plate including a plurality of fluidly isolated, thermally coupled, adjacently nested boustrophedonic channels that terminate in a common upper end and a common lower end. Each turn of each channel includes a top arm and a bottom arm fluidly coupled by a side segment, wherein the top arm is stacked above the bottom arm along the height of the cold plate. An outlet manifold is fluidly coupled to the common upper end of the plurality of channels and an inlet manifold is fluidly coupled to the common lower end the plurality of channels, wherein the inlet manifold is disposed below the outlet manifold to facilitate an upward coolant flow path.

Abstract: Various embodiments disclose a system and an associated method to provide cooling to a plurality of electronic components mounted proximately to one another in an electronic enclosure is disclosed. The system comprises a cold plate that is mounted on the electronic enclosure to conduct heat thermally. The cold plate has a first surface to mount proximate to the plurality of electronic components and a second surface to mount distal from the plurality of electronic components. One or more heat risers are configured to be thermally coupled between the first surface of the cold plate and at least one of the plurality of electronic components.

Abstract: Various embodiments disclose a system and method to provide cooling to electronic components, such as electronic modules or the like. The system includes one or more cold plates that are configured to be thermally coupled to one or more of the electronic components. Internally, each of the cold plates has a cooling fluid flowing inside of at least one passageway. The cooling fluid thus removes heat from the electronic components primarily by conductive heat transfer. An input and an output header are attached to opposite ends of the passageway to allow entry and exit of the cooling fluid. The input and output headers are attached to an external system to circulate the cooling fluid.

Abstract: Various embodiments disclose a system and method to provide cooling to electronic components, such as electronic modules or the like. The system includes one or more cold plates that are configured to be thermally coupled to one or more of the electronic components. Internally, each of the cold plates has a cooling fluid flowing inside of at least one passageway. The cooling fluid thus removes heat from the electronic components primarily by conductive heat transfer. An input and an output header are attached to opposite ends of the passageway to allow entry and exit of the cooling fluid. The input and output headers are attached to an external system to circulate the cooling fluid.

Abstract: Various embodiments disclose a system and method to provide cooling to electronic components, such as electronic modules or the like. The system includes one or more cold plates that are configured to be thermally coupled to one or more of the electronic components. Internally, each of the cold plates has a cooling fluid flowing inside of at least one passageway. The cooling fluid thus removes heat from the electronic components primarily by conductive heat transfer. An input and an output header are attached to opposite ends of the passageway to allow entry and exit of the cooling fluid. The input and output headers are attached to an external system to circulate the cooling fluid.

Abstract: Multicast is performed in a packet-based network switch having a switch fabric of store-and-forward switch nodes. Congestion and blocking at an ingress port is avoided because packet replication is performed at random nodes dispersed throughout the switch fabric. Each multicast packet inserted into the switch fabric by the ingress port is sent to a randomly-selected node. The random node replicates the multicast packet into many unicast packets that are routed to egress ports. A SONET frame can be divided into several multicast packets that are dispersed to different random nodes before replication, thus dispersing congestion. Replication can be delayed until the next SONET frame to prevent latency build up from propagation delays in the switch fabric. Alternately, the SONET payload envelope pointer can be advanced by the propagation delay. Lookup tables at the random nodes can include a list of destinations so that all the destination addresses do not have to be stored in each multicast packet header.

Abstract: A large network switch has switch elements distributed across several chassis separated by perhaps several hundred meters. A generated sync pulse arrives at different switch elements at different times, creating skew. The latency of data through the network switch is set to match the frame period of SONET frames. SONET frames are adjusted at the ingress ports to align the data pointer to the beginning of the frame. The frame is divided along row boundaries into separate cell-packets that are routed across the switch fabric to the egress port. The packets are held in a buffer at the egress port until the next frame begins with the next sync pulse. Upon receiving the next sync pulse, the frame is transmitted. No pointer adjustment is needed by the egress port. A row number is used as a sequence number for the cell-packet to allow the egress port to re-order the cell-packets when transmitting the frame. Since no pointer manipulation is needed at the egress port, pointer management is simplified.

Abstract: An interconnection network routes packets among switches connected in a multi-dimensional network of links. Each packet contains a header with an address of a source switch connected to an input port that receives the packet, and a destination switch connected to an output port that transmits the packet. Each packet header also contains a random address of a random switch in the network. The packet is first routed from the source switch toward the random switch. Then a phase flag in the header is cleared by the random switch, and the packet is routed toward the destination switch. If a faulty link or switch is encountered, and no known routes are available to the destination, the phase flag is again set and another random address generated. The packet is then routed to a new random switch, bypassing the fault.

Abstract: A programmable interconnect cell for selectively connecting circuit nodes of a field programmable integrated circuit array in a semiconductor substrate includes a switch field effect transistor, a sense field effect transistor, and an electron tunneling device with the transistors and electron tunneling device having interconnected floating gates and interconnected control gates. The floating gates comprise a first polysilicon layer which is restricted to each cell, and the control gates comprise a second polysilicon layer which extends to adjacent cells in the row. The source/drain regions of the sense transistor extend to source/drain regions of sense amplifiers in adjacent rows. Programming and erasing of the switch transistor is effected entirely by electron tunneling in the electron tunneling device.

Abstract: The present invention provides for a programming portion of an FPGA cell of an integrated circuit and a process of manufacturing the programming portion. The programming portion has an EPROM transistor and a separated select transistor with the gate of the select transistor connected to the control gate of the EPROM transistor. Both transistors share a common N+ source/drain region, which is self-aligned with the gates of both transistors. With the select transistor separated from the EPROM transistor and the self-aligned common N+ region, the threshold voltage V.sub.T of the select transistor can be set precisely. This allows good control over the programming voltage for the control gate of the EPROM transistor and the time to program the floating gate of the EPROM transistor.

Abstract: A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.

Abstract: A novel method of connecting and operating an NVM transistor in the switching circuit is provided. A full voltage signal can be switched across an NVM transistor. The device is turned on prior to the signal switching and the electrical characteristics of the NVM device relative to the associated circuitry is carefully regulated to prevent the source-drain voltage from rising above a preselected maximum voltage (e.g. 1 v). Two embodiments of the present invention are described. In the first embodiment, the relative impedances of the NVM transistor and its driving circuit are controlled. The driver circuit and the NVM transistor switch act as a resistor divider circuit with a percentage of the full switching voltage appearing across the NVM transistor and the driver circuit according to their relative impedances. The second embodiment is applicable when the NVM transistor switch drives a capacitive load. The rise time of the signal to be switched is controlled.

Abstract: Various methods and apparatus perform IDDQ testing using the input and output circuits typically associated with input and output pads of an integrated circuit. Under these methods, the number of tester channels and external circuit elements required for IDDQ measurements is minimized. In one embodiment, the IDDQ current is measured by sensing the voltage at either an input pad or an output pad. In another embodiment, an internal pull-up transistor of known resistance is used for current sensing. In another embodiment, a method and apparatus for performing IDDQ testing quickly are provided by disconnecting the primary power or ground bus line connections from the tester and using alternate connections to provide power to the circuit under test over the duration of the IDDQ testing.

Abstract: An output buffer and a method provide controlled low noise operation using a current mirror which provides a rapid increase in the gate voltage of an output transistor prior to the gate voltage reaching the threshold voltage of the output transistor and provide a constant current voltage ramp thereafter. In one embodiment, the present invention automatically compensates for normal variations in transistor channel length due to fluctuations of process parameters. In one embodiment, a mechanism for switching off the current mirror is provided to reduce power consumption.

Abstract: This invention provides a means to interconnect high performance CMOS VLSI circuits. LTL (a coined descriptor for describing a novel CMOS interface standard) offers improved performance by providing active threshold control of an input buffer to speed signal capture, and by controlling performance limiting characteristics of signal reflection, ground bounce, receiver overdriving and ringing. These performance limiting characteristics are controlled by providing: level-sensitive impedance control of an output driver, distributed active line termination using impedances of input buffers on a transmission line, and balanced loading using closed-loop transmission lines.

Abstract: A method and an apparatus to heat an integrated circuit and regulate its temperature for the purposes of burn-in and temperature testing are provided. The circuit is heated internally by integrating a heating means. Sensing and controlling means may also be integrated. Such heating and controlling are activated by external signals applied to the IC. Practical means to heat the integrated circuit with pre-existing components is provided.

Abstract: A method for operating a multiple input linear feedback shift register (LFSR) as a conventional shift register so that input multiplexers can be eliminated on each parallel input when associated with a CrossCheck matrix. A linear feedback shift register coupled through sense lines of a CrossCheck test matrix is operated as a serial shift register by inputting serial data at the serial data input while maintaining parallel input lines at a zero logic level. Further, zero logic level serial data (null data) is input serially through the shift register prior to the enabling of the parallel input. The method significantly reduces the number of logic structures required to shift the data out serially.

Abstract: An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output "one" minimum level (VOH) or output "zero" maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults.