Abstract: Various methods and apparatus perform IDDQ testing using the input and output circuits typically associated with input and output pads of an integrated circuit. Under these methods, the number of tester channels and external circuit elements required for IDDQ measurements is minimized. In one embodiment, the IDDQ current is measured by sensing the voltage at either an input pad or an output pad. In another embodiment, an internal pull-up transistor of known resistance is used for current sensing. In another embodiment, a method and apparatus for performing IDDQ testing quickly are provided by disconnecting the primary power or ground bus line connections from the tester and using alternate connections to provide power to the circuit under test over the duration of the IDDQ testing.

Abstract: An output buffer and a method provide controlled low noise operation using a current mirror which provides a rapid increase in the gate voltage of an output transistor prior to the gate voltage reaching the threshold voltage of the output transistor and provide a constant current voltage ramp thereafter. In one embodiment, the present invention automatically compensates for normal variations in transistor channel length due to fluctuations of process parameters. In one embodiment, a mechanism for switching off the current mirror is provided to reduce power consumption.

Abstract: This invention provides a means to interconnect high performance CMOS VLSI circuits. LTL (a coined descriptor for describing a novel CMOS interface standard) offers improved performance by providing active threshold control of an input buffer to speed signal capture, and by controlling performance limiting characteristics of signal reflection, ground bounce, receiver overdriving and ringing. These performance limiting characteristics are controlled by providing: level-sensitive impedance control of an output driver, distributed active line termination using impedances of input buffers on a transmission line, and balanced loading using closed-loop transmission lines.

Abstract: A method and an apparatus to heat an integrated circuit and regulate its temperature for the purposes of burn-in and temperature testing are provided. The circuit is heated internally by integrating a heating means. Sensing and controlling means may also be integrated. Such heating and controlling are activated by external signals applied to the IC. Practical means to heat the integrated circuit with pre-existing components is provided.

Abstract: A method for operating a multiple input linear feedback shift register (LFSR) as a conventional shift register so that input multiplexers can be eliminated on each parallel input when associated with a CrossCheck matrix. A linear feedback shift register coupled through sense lines of a CrossCheck test matrix is operated as a serial shift register by inputting serial data at the serial data input while maintaining parallel input lines at a zero logic level. Further, zero logic level serial data (null data) is input serially through the shift register prior to the enabling of the parallel input. The method significantly reduces the number of logic structures required to shift the data out serially.

Abstract: An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output "one" minimum level (VOH) or output "zero" maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults.

Abstract: A monolithic integrated complementary metal oxide semiconductor (CMOS) circuit senses internal junction temperature and converts it to a binary coded decimal output signal. The circuit compares a temperature dependent junction voltage with a bandgap reference voltage controlled by a very stable amplifier. The comparison differential is then converted to a binary coded decimal output signal by an analog to digital converter. The circuit utilizes parasitic bipolar NPN transistor elements formed from a substrate of the chip in a conventional CMOS fabrication process. The principles of the present invention are also broadly applicable to other semiconductor technologies such as integrated injection logic (I.sup.2 L).