Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.

Abstract: A circuit for attenuating a signal has an input configured to receive an input signal, an output configured to transmit an output signal, a first attenuation path (having a first active circuit device) between the input and the output, and a second attenuation path between the input and the output. The circuit also has an operational amplifier that, like most operational amplifiers, has a first op-amp input, a second op-amp input, and an op-amp output. In addition, the circuit has a voltage control device coupled with the first op-amp input, and a second active circuit device having a first active terminal coupled with the second op-amp input. A feedback loop is coupled between the op-amp output and a second active terminal of the second active circuit device. Moreover, the op-amp output also is coupled with the first active circuit device.

Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

Abstract: An integrated circuit system has a die with first and second sides, and contains high frequency circuitry operating at mm-wave frequencies. The system also has a plurality of interfaces (on the first side) in electrical communication with the high frequency circuitry, and a heat sink having a bottom surface with a first region and an aperture region. The first region is in physical and conductive contact with the die, while the aperture region forms a concavity with an inner concave surface that is spaced from the die.

Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).

Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

Abstract: A circuit for attenuating a signal has an input configured to receive an input signal, an output configured to transmit an output signal, a first attenuation path (having a first active circuit device) between the input and the output, and a second attenuation path between the input and the output. The circuit also has an operational amplifier that, like most operational amplifiers, has a first op-amp input, a second op-amp input, and an op-amp output. In addition, the circuit has a voltage control device coupled with the first op-amp input, and a second active circuit device having a first active terminal coupled with the second op-amp input. A feedback loop is coupled between the op-amp output and a second active terminal of the second active circuit device. Moreover, the op-amp output also is coupled with the first active circuit device.

Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

Abstract: A beamforming integrated circuit system for use in a phased array has a microchip with RF circuitry, and a plurality of (on chip) interfaces electrically connected with the RF circuitry. The plurality of interfaces includes a signal interface, a first ground interface, and a second ground interface. The signal interface is configured to communicate an RF signal, and both the first and second ground interfaces are adjacent to the signal interface. The system also has a material ring circumscribing the plurality of interfaces, and at least one RF ground path coupled with the material ring.

Abstract: A beamforming integrated circuit system for use in a phased array has a microchip with RF circuitry, a bottom surface, and a plurality of interfaces electrically connected with the RF circuitry. The plurality of interfaces includes a plurality of static interfaces and a plurality of RF interfaces. The plurality of static interfaces are on the bottom surface of the microchip and adjacent to each other. The plurality of RF interfaces are also on the bottom surface of the microchip, but radially outward of the plurality of static interfaces. The microchip is configured to be flip chip mounted.

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: An RF power amplifier operates over the range of supply voltages provided by a DC/DC converter whether the range of voltages is intentional or unintentional. A system for digitally adjusting the bias levels relative to the supply voltage includes at least one RF power amplifier stage, a digital control block, and a bias circuit. The RF power amplifier stage has at least one RF input signal, at least one RF output signal, and at least one bias input that controls its bias conditions. The RF Power Amplifier Stage includes one or more active gain elements used to amplify the RF input signals. The RF power amplifier operates in a number of bias states controlled by the digital control block. The digital control block uses information related to the supply voltage and may use other information stored in memory to select the desired bias.

Abstract: An RF power amplifier operates over the range of supply voltages provided by a DC/DC converter whether the range of voltages is intentional or unintentional. A system for digitally adjusting the bias levels relative to the supply voltage includes at least one RF power amplifier stage, a digital control block, and a bias circuit. The RF power amplifier stage has at least one RF input signal, at least one RF output signal, and at least one bias input that controls its bias conditions. The RF Power Amplifier Stage includes one or more active gain elements used to amplify the RF input signals. The RF power amplifier operates in a number of bias states controlled by the digital control block. The digital control block uses information related to the supply voltage and may use other information stored in memory to select the desired bias.

Abstract: A radio frequency output power control system is disclosed for use in communication systems that use a modulation scheme having a non-constant amplitude envelope. The system includes a power amplifier having a radio frequency input node for receiving a radio frequency input signal, a power control node for receiving a filtered power control signal, and an output for providing an amplified output signal. The system also includes a variable filter that receives a power control signal at a power control input and a receives a trigger signal at a trigger input, and provides a filtered power control signal to the power control node of the power amplifier responsive to the power control signal and the trigger signal.

Abstract: An amplifier stage capable of delivering a peak limited voltage pulse with sharp transitions, at a desired width and duty cycle, and with high efficiency is disclosed. One disclosed embodiment relates to a circuit that includes a tuned class D amplifier that receives an input signal and generates a pulsed RF output signal in response to the input signal. The pulsed RF output signal has a greater power than that of the input signal.

Abstract: An amplifier stage capable of delivering a peak limited voltage pulse with sharp transitions, at a desired width and duty cycle, and with high efficiency is disclosed. One disclosed embodiment relates to a circuit that includes a tuned class D amplifier that receives an input signal and generates a pulsed RF output signal in response to the input signal. The pulsed RF output signal has a greater power than that of the input signal.

Abstract: Systems and methods for switching electronic signals are disclosed. The switching may be performed with a low loss and low peak voltages. The switching scheme is suitable for switching RF signals, for example, and may be used in devices such as wireless systems, terminals, and handsets. One exemplary embodiment is directed to a CMOS-implemented transmit/receive switching system. The system comprises one or more transmit ports, each coupled via a respective transmit path to an input/output port and one or more receive ports, each coupled via a respective receive path to the input/output port. Each receive path comprises a switching circuit comprising a transistor and an inductor in parallel with the transistor. The switching circuit is adapted to at least substantially isolate the respective receive port from the input/output port when the transistor is in an on state and operatively couple the respective receive port to the input/output port when the transistor is an off state.

Abstract: Exemplary techniques for implementing an amplifier suitable for RF amplification, such as a tuned class DE amplifier, are disclosed. One disclosed embodiment of a circuit for amplifying an RF signal includes a push-pull amplifier comprising a push transistor and a pull transistor. A first driver amplifier drives the push transistor of the push-pull amplifier with a first RF signal. A second driver amplifier drives the pull transistor of the push-pull amplifier with a second RF signal different from the first RF signal.