Abstract: Methods and systems for forming multigate devices and systems are disclosed. In accordance with one such method, a fin is formed on a semiconductor substrate including a carbon-doped semiconductor layer. Further, a first portion of semiconductor material that is beneath the fin is removed to form a void beneath the fin by etching the material such that the fin is supported by at least one supporting pillar of the semiconducting material and such that the carbon-doped semiconductor layer prevents the etching from removing at least a portion of the fin. A dielectric material is deposited in the void to isolate the fin from a second portion of semiconductor material that is below the void. In addition, source and drain regions are formed in the fin and a gate structure is formed over the fin to fabricate the multigate device such that the dielectric material reduces current leakage beneath the device.

Abstract: A multiferroic element may include a substrate formed on an electrically conductive ground plane. The substrate may be formed from a material having a predetermined elastic modulus. A layer of piezoelectric material may be formed on the substrate. A layer of magnetostrictive material may be bonded to the layer of piezoelectric material. A mechanical strain is created in the layer of piezoelectric material in response to a voltage signal being applied to the multiferroic element. The mechanical strain in the layer of piezoelectric material causes a mechanical strain in the layer of magnetostrictive material to produce a radio frequency magnetic field that is proportional to the voltage signal for generating a radio frequency electromagnetic wave. The predetermined elastic modulus of the substrate is substantially lower than an elastic modulus of the layer of piezoelectric material.

Abstract: A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and overall silicon volume for improved heat dissipation during an ESD event.

Abstract: Dendrimers comprising N-acyl urea terminal moieties are described herein. The dendrimers can be used, for example, in the treatment of arthritis.

Abstract: A multiferroic antenna and sensor where the sensor includes a multiferroic stack of multiple connected multiferroic layer-pairs, each multiferroic layer-pair comprising an alternating layer of a magnetostrictive material and a piezoelectric material bonded together enabling a high signal sensitivity, a magnetic field of an incident signal causing mechanical strain in the magnetostrictive material layers that strains adjacent piezoelectric material layers producing an electrical voltage in each multiferroic layer-pair proportional to the incident signal. An output of the multiferroic stack comprises the electrical voltage amplified proportional to a total number of multiple connected multiferroic layer-pairs in the multiferroic stack.

Abstract: One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.

Abstract: Disclosed herein is a structural sheet includes an energy storage density that is greater than 10-mWh/ft2 and is capable of withstanding greater than 5-KPa stress under at least 5% strain. Further provided is an energy storing structural sheet comprising an electrically conducting current carrying layer that is print formed over a sub assembly that comprises a separator, a foundation, an electrode, and a current bus.

Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

Abstract: A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.

Abstract: One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.

Abstract: Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.

Abstract: Dendrimers comprising N-acyl urea terminal moieties are described herein. The dendrimers can be used, for example, in the treatment of arthritis.

Abstract: An energy storing and dispensing sheeting having addressable energy storing cells is disclosed. A free-forming process of fabricating energy storing sheets is disclosed. An interconnect interface for operatively coupling the energy storing sheeting to an external element is disclosed. A flexible printed circuit board with patterned energy storing layers is disclosed. An adhesive, flexible energy storing sheeting is disclosed. Energy storing sheet that can be mechanically tuned and patterned as a structural building material is disclosed. A networked grid storage embodiment of a structural energy storing sheeting is disclosed. An energy storing sheeting powering computer memory and integrated circuits is disclosed. A puncture tolerant energy storage device is disclosed. An ultracapacitor having a separator, symmetric or asymmetric electrodes, electrolyte and a current collector is disclosed. A battery, supercapacitor and hybrid device is disclosed.

Abstract: Semiconductor device fabrication methods having enhanced control in recessing processes are provided. In a method for fabricating a semiconductor device or plurality of them, a structure is formed. The method includes preparing a limited amount of the structure having a depth of less than ten atomic layers for removal. Further, the method includes performing a removal process to remove the limited amount of the structure. The method repeats preparation of successive limited amounts of the structure for removal, and performance of the removal process to form a recess at an upper portion of the structure.

Abstract: Sensing strain in an adhesively bonded joint includes inducing a strain wave in the joint, and sensing a change in local magnetic characteristics in the joint. An array includes a plurality of elements for sensing and inducing a strain wave in selected regions of a structure having the adhesively bonded joint. The elements include at least one micromechanical driver for inducing strain waves in selected regions, a plurality of mechanical sensors for measuring vibrations resulting from the induced strain waves, a plurality of micromagnetic drivers for generating weak magnetic fields over the selected regions, and a plurality of micromagnetic sensors for sensing magnetic responses of the selected regions to the strain waves.

Abstract: Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.

Abstract: The present invention relates to a heparin-derivatized collagen matrix comprising a fragment of heparin covalently linked to a collagen scaffold, wherein the fragment of heparin has molecular weight of less than about 15 kDa, and at least one heparin-binding growth factor (HBGF) or heparin-binding adeno-associated virus (HB-AAV) or a combination thereof and methods for promoting bone growth, bone repair, cartilage repair, bone development, neo-angiogensis, wound healing, tissue engraftment and muscle tissue regeneration and/or tissue augmentation comprising administering a heparin-derivatized collagen matrix that includes at least one heparin-binding growth factor or heparin-binding adeno-associated virus or a combination thereof.

Abstract: Disclosed herein is a structural sheet includes an energy storage density that is greater than 10-mWh/ft2 and is capable of withstanding greater than 5-KPa stress under at least 5% strain.

Abstract: A method of manufacturing a finned semiconductor device structure is provided. The method begins by providing a substrate having bulk semiconductor material. The method continues by forming a semiconductor fin structure from the bulk semiconductor material, depositing an insulating material overlying the semiconductor fin structure such that the insulating material fills space adjacent to the semiconductor fin structure, and planarizing the deposited insulating material and the semiconductor fin structure to create a flat surface. Thereafter, a replacement gate procedure is performed to form a gate structure transversely overlying the semiconductor fin structure.

Abstract: A second optional poker tournament fee allows participating players a chance to receive a payout when finishing the poker tournament in one of one or more extra bubble spots. So, if the player finishes close to the conventional bubble position the player may receive a payout if he or she paid the second optional fee. The number of extra spots is based on the number of second optional fees paid. In one version, if no players finish in the extra bubble spots the house collects the second optional fees as profits. In another version, the second optional fees, or a portion thereof, are used to increase the payouts associated with the conventional payout scheme independent of the second optional fees.