Abstract: Described embodiments provide a network processor having a hardware accelerator that identifies a received packet and, based on a flow identification associated with the received packet, might pre-fetch pre-established portions of data from the received packet into local data memory (e.g., local data cache) for processing by a general purpose processor core. In addition to the packet data, the software necessary for the general-purpose processor core to process the data might also be pre-fetched into local instruction memory (e.g., local instruction cache). The flow identification might be used to select different portions of the packet and different software to be pre-fetched.

Abstract: Described embodiments provide for a reassembly system for processing an asynchronous transfer mode (ATM) cell of data into an ATM adaptation layer (AAL) packet. A preprocessor module identifies a first conversation identification of one or more minipackets in the ATM cell, and reassembles the one or more minipackets having the first conversation identification into a portion of the AAL packet. A preprocessor determines if a trigger has occurred. In response to a trigger, the preprocessor sends a portion of the reassembled minipackets having the first conversation identification to a destination processor.

Abstract: Described embodiments provide a system having at least two network processors that each have a plurality of processing modules. The processing modules process a packet in a task pipeline by transmitting task messages to other processing modules on a task ring, the task messages related to desired processing of the packet. A series of tasks within a network processor may result in no processing or reduced processing for certain processing modules creating a virtual pipeline depending on the packet received by the network processor. At least two of the network processors communicate tasks. This communication allows ter the extension of the virtual pipeline of or IC network processor to at least two network processors.

Abstract: Described embodiments provide for processing received data packets into packet reassemblies for transmission as output packets of a network processor. A packet assembler determines an associated packet reassembly of data portions and enqueues an identifier for each data portion in an input queue corresponding to the packet reassembly associated with the data portion. A state data entry corresponding to each packet reassembly identifies whether the packet reassembly is actively processed by the packet assembler. Iteratively, until an eligible data portion is selected, the packet assembler selects a given data portion from a non-empty input queue for processing and determines if the selected data portion corresponds to a reassembly that is actively processed. If the reassembly is active, the packet assembler sets the selected data portion as ineligible for selection. Otherwise, the packet assembler selects the data portion for processing and modifies the packet reassembly based on the selected data portion.

Abstract: A network processor for determining one or more network operations to be performed on a packet of data in a network comprises processing circuitry and protocol indicator circuitry. The packet of data contains information populating a plurality of protocol header fields. Moreover, the protocol indicator circuitry comprises a plurality of memory elements, each memory element associated with a protocol header field in the plurality of protocol header fields. The processing circuitry determines the one or more network operations to be performed on the packet of data at least in part by addressing one or more lookup tables with the contents of a subset of the plurality of protocol header fields in the packet. This subset is determined by reference to the memory elements in the protocol indicator circuitry. Each memory element is capable of being programmed to indicate whether the associated protocol header field is to be utilized by the processing circuitry in addressing the one or more lookup tables.

Abstract: Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Abstract: A network device comprises a plurality of lookup tables and a processor. Each of the plurality of lookup tables comprises a plurality of table inputs that are associated with a plurality of processor instructions. The processor is operative to perform a network operation on a packet of data comprising a plurality of protocol header fields at least in part by performing one or more lookup cycles. A lookup cycle comprises the addressing of one of the plurality of lookup tables with one of the plurality of table inputs and the performing of the processor instruction associated with that table input. At least one of the plurality of processor instructions in the plurality of lookup tables comprises an instruction directing that the content of one of the plurality of protocol header fields be read and that one of the plurality of lookup tables be addressed with that content as the table input.

Abstract: A network device is operative to perform different network operations on a packet of data in a network. The packet of data has a packet payload comprising one or more encoded characters. A lookup table comprises a plurality of table entries. Packet processing circuitry coupled to the lookup table determines which of the different network operations to perform on the packet of data at least in part by addressing the lookup table with a table input. The table input comprises one or more characters from the packet payload. The table entry corresponding to the table input is determined by a longest prefix match algorithm.

Abstract: An address interworking system and method for an internetwork that includes a first network using first network addressing communicating via one or more internetworking gateways with a second network using second network addressing. The gateways register one or more first network addresses in the second network as first network address-encapsulated or- mapped second network addresses. Reachability information regarding the first network-encapsulated or -mapped second network addresses is then disseminated through the second network. When a communication request containing a first network destination address is received from the first network at one of the gateways, the receiving gateway performs encapsulation or mapping of the first network destination address into a first network-encapsulated or -mapped second network destination address.

Abstract: A telephone networking system includes a database having executable programs which are equivalent to customer record programs used by a SCP. A switching device retrieves one of the executable programs from the database in response to data received by an input device, such as a telephone. The executable program is transmitted across the network to be executed by an edge device having the capability to store information and perform logical operations. For an 800/888 telephone call, the executable program instructs the edge device to request and gather additional information. The additional information is then used by the executable program to generate the POTS number which is transmitted to the switching device to complete the call.