Abstract: A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit.

Abstract: A dynamic random access memory (10) is fabricated on a substrate (12) and is divided into memory sections (14, 16). Memory cells (46) are connected to bit lines (18-28, a and b), which are organized into pairs that are connected to respective sense amplifiers (34-44). A row clock circuit (52) generates clock signals to enable the addressed word line. Additional clock signals are generated by other clock circuits (56, 58). A charge pump circuit (78, 80) produces a substrate bias and includes a free running oscillator. The signal generation circuits (52, 56, 58, 78, 80) produce signal transitions which are coupled by parasitic capacitors (66-76, 81-88) into the bit lines (18-28, a and b). The clock circuits are fabricated in a symmetrical placement in relation to the bit lines (18-28, a and b) and sense amplifiers (34-44) such that the transient signals capacitively coupled from the clock circuits into the bit lines have a very low differential mode amplitude.

Abstract: A semiconductor memory circuit (140) includes a plurality of memory cells each having an access transistor (154, 158) and a storage capacitor (162, 166). The memory cells are connected to digit lines (142, 144) each of which is split into halves each connected to one input of a sense amplifier (146, 148). The sense amplifiers (146, 148) operate to pull one of the half digit lines connected thereto to ground while a pull up circuit (220) operates to elevate the other half digit line to the supply voltage. A margin test circuit receives through a control pin (236) an externally supplied test command which generates a test signal (318) to generate marginal low and marginal high voltage states to be written into the memory cells. The marginal low voltage state is generated by a voltage divider (288). The marginal high voltage state is generated by disabling the pull up circuit (220).

Abstract: A dynamic random access memory cell (30) includes an access transistor (32) having the gate terminal thereof connected to a word line (34) and the source and drain terminals thereof connected between a bit line (36) and a node (37). A charge storage capacitor (38) is connected between the node (37) and a decoded plate line (40). The plate line (40) receives a bi-level voltage which shifts levels in a timing sequence keyed to the word line (34) signal. Shifting of voltage levels provided to the capacitor (38) through the plate line (40) essentially doubles the signal margin of the memory circuit (30) to thereby enhance the reliability of the data stored in the memory circuit (30).

Abstract: A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row.

Abstract: A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (V.sub.cc *) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (V.sub.cc *) is the semiconductor memory circuit main supply source (V.sub.cc) in normal operation but can be forced to a different voltage during the margin test.

Abstract: A semiconductor dynamic memory circuit (10) includes a memory cell array (38) which includes a plurality of memory cells which are accessed through row and column lines by operation of row and column clock chain signals. A strap (68) is provided to operate the circuit (10) as either a memory which is refreshed according to internally generated addresses or a memory which is refreshed in response to externally supplied memory addresses and is easily incorporated into a memory system which utilizes error detection and correction during the refresh operation. In the absence of the strap (68) a refresh signal (20) refreshes cells of the array (38) in response to the address generated by an internal address counter (82). The circuit (10) accesses a given memory location when an externally supplied address is provided together with a RAS signal (12) and a CAS signal (16).

Abstract: A quiet line flip-flop is connected to a plurality of lines (12, 14) for reducing the effect of capacitive coupling between the lines (12, 14) and a line (18). A node (26) is precharged by a transistor (34) to render conductive transistors (30, 32) which connect the respective lines (12, 14) to a ground node (24). When either of the lines (12, 14) is forced to a voltage above a preset voltage the corresponding transistors (22, 28) are respectively rendered conductive to discharge the node (26) which causes the transistors (30, 32) to be rendered nonconductive thereby disconnecting the lines (12, 14) from the ground node (24).

Abstract: A dynamic random access memory (10) receives a memory address of a row decoder (14) which charges a selected row line (18). When the row line (18) is charged an access transistor (24) in a memory cell (22) is rendered conductive to connect a storage capacitor (26) to a bit line (30). The bit lines (30, 38) are previously set at an equilibration voltage. The voltage on the bit line (30) is driven slightly above the equilibration voltage if a high voltage state had been stored in the capacitor (26) or the voltage on the bit line is driven slightly below the equilibration voltage if a low voltage state had been stored on the capacitor (26). A sense amplifier (44) is connected to the bit lines (30, 38) and upon receipt of a latch signal (L) drives the one of the bit lines (30, 38) having the lower voltage to a low voltage state. A pull-up circuit (60) drives the voltage on the remaining bit line of the pair to a high voltage state, restoring the memory storage capacitor (26) to its initial state.

Abstract: A burn-in tape (48) includes a backing (50) and a pair of rectangular openings (56, 58) positioned transversely on the backing (50). Power conductors (52, 54) extend longitudinally on backing (50) outboard of the openings (56, 58). Additional conductor lines (104, 106) extend longitudinally along backing (50) between the openings (56, 58). Conductor strips (62, 70, 80, 88) connect the conductors (104, 52, 106, 54) to bonding pads (12, 20, 30, 38) on an integrated circuit (10). Signal conducting strips (64, 66, 68, 72, 74, 76, 78, 82, 84, 86, 90, 92, 94, 96) extend from corresponding test pads on backing (50) to bonding pads on the integrated circuit (10). The backing (50) is provided with sprocket holes (98) for precisely aligning the burn-in tape (48) with the integrated circuit (10). The conductors on the tape (48) provide a means for operating and thereby burning-in the components of the integrated circuit (10).

Abstract: A circuit for burning-in an integrated circuit memory receives a two state signal at a burn-in terminal (168). A clock refresh signal is provided to a refresh terminal (170) which drives a refresh counter (192). A sequence of addresses are generated by the refresh counter (192) and provided to row decoders (194) and column decoders (196). When the burn-in command provided to the burn-in terminal (168) is at a first state, sense amplifiers (132) within a memory array (107) are disabled so that pullup circuits (148) elevate digit lines (116, 118) to a high voltage level. The high voltage level is transferred into memory cell storage capacitors (120, 122). When the burn-in command is in either the first or the second state, the refresh signal causes a row clock chain generator (176) to generate row clock signals and a column clock chain generator (178) to generate column clock signals.

Abstract: A decoder circuit (66) includes a plurality of input transistors (78-86) connected to address lines (68-76). The drain terminals of the input transistors (78-86) are connected to a first power terminal and the source terminals thereof are connected to a first node (92) which is charged to low voltage state upon receipt of a precharge signal at a transistor (94). An address enable signal (58) operates a transistor (96) to connect node (92) to node (98) during receipt of the address. A node (102) is charged to a high state by operation of a transistor (100) in response to a precharge signal (56). Node (102) is discharged through a transistor (104) when a high voltage state is present at the node (98). An enable clock signal (52) is transmitted through a transistor (106) to a row line (108) when a high voltage state is present on node (102).

Abstract: A semiconductor memory decoder (10) includes an OR gate (12) which receives a multi-bit memory address. A node (26) is precharged to a low state and driven to a high state when the OR gate (12) is not selected by the address. A node (34) is precharged to a high state and pulled to ground when the node (26) is driven to a high state. The high state precharged on the node (34) is conveyed to a node (40) which is connected to the gate terminal of a row driver transistor (54) and to a node (46) which is connected to the gate terminal of a row driver transistor (64). The one of the nodes (40,46) not connected to a selected row line is isolated from the node (34) to render conductive the corresponding nonselected row driver transistor (54,64). A high voltage state row driver signal (RD0,RD1) is transmitted through the selected row driver transistor (54,64) to charge the selected row line (56,66).

Abstract: A circuit to permit testing the refresh counter in an integrated circuit memory by writing into cells whose row addresses are determined by the refresh counter.

Abstract: A current limiting driver circuit (10) receives a first logic level input signal (.phi..sub.1) and drives an output pin (26). A node (14) is pulled to ground by a pull-down transistor (16) which receives the first input signal (.phi..sub.1) and is driven to a high voltage state by a pull-up transistor (12). A driver transistor (28) is turned on by a high voltage state at the node (14) and is turned off by a low voltage state at the node (14). The driver transistor (28) is connected to provide a high voltage state to the output pin (26). A pull-down transistor (30) is connected to receive the first input signal (.phi..sub.1) in order to pull the output pin (26) to ground.

Abstract: A method for operating a dynamic semiconductor memory circuit (10) having a memory cell (12) which comprises a access transistor (12a) connected to a half digit line (18) and a storage capacitor (12b). Each of the half digit lines (18, 22, 60 and 62) is charged or discharged as a result of either read operations carried out with the corresponding memory cells or write operations receiving incoming data states through input/output lines (42, 46). The charged state of the half digit line (18, 22, 60 and 62) is at a voltage substantially below that of the supply voltage of the circuit (10). After the half digit lines (18, 22, 60 and 62) are sensed and/or written to the desired states, a pullup circuit (48) for each of the half digit lines (18, 22, 60 and 62) charges the half digit lines with voltages above a predetermined threshold to the full supply voltage.

Abstract: A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row.

Abstract: An input buffer for MOSFET integrated circuit for receiving low level voltage signals even below the threshold voltages of the transistors comprising the circuit is described. A reference voltage between two logic levels of the input voltage, such as TTL logic signals of 0.8 volts and 1.8 volts, is trapped on a reference storage node and the logic input voltage is trapped on a data input storage node. The two trapped voltages are then capacitively boosted by the same voltage to a level well above the transistor threshold voltage so that the differences in the voltage levels can be amplified, and the logic signal latched up by conventional circuitry. The voltage levels need be only momentarily boosted above the threshold level.

Abstract: A clock generator for an MOSFET integrated circuit having a plurality of cascaded delay stages is disclosed. Each delay stage includes a bootstrap inverter having first and second transistors connected in series between the drain supply voltage and a source supply voltage, thus forming a first node between the transistors. The first node is capacitively coupled to a bootstrap node which is connected to the gate of the first transistor. The bootstrap node is also coupled through the channel of a third transistor to an input. The gate of the third transistor forms a third node. Circuit means are provided for precharging the third node and then isolating the third node while an input signal is applied through the third transistor to the bootstrap node so that the third node is also bootstrapped up to permit rapid charging of the bootstrap node to the full voltage of the input signal.

Abstract: An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a complement digit line. The true and complement digit lines are each connected through a separate transistor, which functions as a variable resistance, to true and complement input nodes of a sense amplifier. The sense amplifier is comprised of a transistor connecting each input node to a latch node, with the gates of the transistors cross coupled to the opposite input nodes. The digit lines are precharged to equal voltages corresponding to V.sub.DD. When enabled by an address signal, a storage cell is connected to one of the digit lines at the same time a dummy cell is connected to the other digit line. As a result, one of the digit lines has a slightly higher voltage than the other.