Abstract: A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word.

Abstract: A high performance random access memory integrated circuit is disclosed in several embodiments, along with various embodiments of associated supporting circuitry, which offers significant power savings in read operations. The integrated circuit is capable of retrieving data words from a memory array either one data word in a single clock cycle or more than one data word in a single clock cycle. For random memory reads, retrieving one data word from the memory array in a clock cycle where the memory array is accessed in response to each read request saves power over retrieving more than one data word from the memory array in the clock cycle. Conversely, if read requests are burst requests (i.e., a first read request immediately followed by advance requests), power is saved by retrieving more than one data word in a clock cycle where the memory array is accessed.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: Methods of controlling memory buffers having tri-port cache arrays therein include the steps of reading data from a current read register in the cache memory array to an external peripheral device, and writing data from an external peripheral device to a current write register in the cache memory array. Tri-port controller logic and steering circuitry are also preferably provided for performing efficient read and write arbitration operations to make next-to-read and next-to-write registers always available in the cache memory array. The use of four separate registers in the cache memory array, efficient steering circuitry and the tri-port controller logic essentially eliminates the possibility that gaps or stoppages will occur in the flow of data into and out of the buffer memory device during read and write operations.

Abstract: A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. In an exemplary embodiment during an internal write operation, write circuitry supplies a small differential voltage to the selected bit line sense amplifiers, which “swallows” the normal read signal, before bit line sensing. The bit line sense amplifiers then “write” the level into the memory cell during normal latching. This provides for internal write operations which proceed, for many embodiments, at the same speed as internal read operations by letting a selected bit line sense amplifier restore the voltage levels onto the selected bit lines in accordance with the data to be written, rather than in accordance with the data previously stored in a selected memory cell.

Abstract: A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. An exemplary 18 MBit memory array includes four banks of arrays. Within each memory bank, a row of bit line sense amplifiers is implemented in the holes between each pair of array blocks. After a selected word line is driven active, and a signal from each associated memory cell is developed on the corresponding bit line pair, both PMOS and NMOS sensing of the associated bit line sense amplifiers are simultaneously enabled. The PMOS sense amplifier drives the bit line having a higher voltage toward VDD, but this PMOS sensing is terminated before the high-going bit line substantially reaches the full VDD voltage, thus allowing the bit line to quickly be driven to a high level with a reduced “exponential tail.

Abstract: A high performance dynamic memory array architecture includes a row of bit line sense amplifiers between array blocks. Each bit line sense amplifier is shared between two pairs of bit lines. Half of the bit line pairs within each array block are served by a sense amplifier located above the array block, and the remaining half are served by a sense amplifier located below the array block. A read amplifier in the read path, which is separate from the bit line sense amplifier, is used to develop signal on a bus line before bit line sensing has occurred. This read amplifier may be connected to the bit lines, the internal sense amplifier nodes, a local I/O line, or a local output line. In a preferred embodiment, a second stage amplifier further buffers the signal and drives a pair of global output lines which extend the full height of the memory bank to respective I/O circuits.

Abstract: A novel crossover arrangement reduces the area of a memory array by using only one crossover structure within each array block. Yet the total differential signal degradation for each respective true and complement bit line pair arising from coupling between the respective true bit line and the respective complement bit line as well as differential coupling to the respective true and complement bit lines from unrelated adjacent true or complement bit lines, is no worse than that resulting from a true bit line being adjacent to its complement bit line for their entire length. For one embodiment of the invention, each complementary pair of bit lines runs vertically within an array block from the top to the bottom of the array block. The true bit line and complement bit line of a first pair run adjacent to each other from the top to the bottom of the array block without any crossovers.

Abstract: A sense amplifier having four NMOS transistors and two resistors is operable at voltage supplies less than 2.5 volts and has a fast response time. The drain terminals of two of the NMOS transistors, each receiving an input voltage signal at its gate terminal, provide a differential output voltage signal across the two resistors. The source terminals of these two NMOS transistors are coupled to the drain and gate terminals of a cross-coupled second pair of NMOS transistors. The amplifier exhibits negative input capacitance at each of its input terminals. The amplifier has a common mode input voltage that is substantially equal to the common mode output voltage, facilitating the cascading of many stages of the amplifier. Each stage of a multi-stage cascade of the amplifiers has a greater than unity voltage gain if driving a low capacitance line or a smaller than unity gain if driving a high capacitance line.

Abstract: Surface area of a semiconductor integrated circuit memory required by programmable fuse boxes is reduced, and the capacitive loading of a column address bus from the programmable fuse boxes is reduced by reducing the number of programmable boxes. Each programmable fuse box is connected through fuses to a plurality of redundant columns in memory arrays whereby any one or more of the redundant column lines can be addressed through the programmed fuse box in replacing a defective column line. An unprogrammed redundant column select line is connected to ground through the fuses connecting the unselected redundant column select lines to ground so that unprogrammed redundant columns are inactive.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: A circuit and method are provided for disabling a defective normal element using a flip-flop. The flip-flop has two states. In a first state, the flip-flop enables a normal decoder, corresponding to the normal element, to respond to a respective address for the normal element. In a second state, the flip-flop disables the normal decoder from responding to any address.

Abstract: A circuit and method are provided for disabling a defective normal element using a flip-flop. The flip-flop has two states. In a first state, to which the flip-flop can be set on application of power, the flip-flop enables a normal decoder, corresponding to the normal element, to respond to a respective address for the normal element. In a second state, to which the flip-flop can be set only upon coincident selection of a defective normal element and a programmed redundant element during an initialization routine, the flip-flop disables the normal decoder from responding to any address.

Abstract: An exemplary 18 MBit memory array includes four banks of array blocks. At the end of an active cycle, the exemplary memory array is automatically taken back into precharge without waiting for a control signal. One edge of a clock causes the memory array to execute a useful cycle, then to automatically reset itself in preparation for a new cycle, preferably using two sets of precharge signals- one is an automatically timed pulse, while the other stays on until the start of the next cycle. Both turn on automatically at the same time just after the selected word line is brought low. One equilibrate signal is turned off by a timed pulse just when the bit line equilibration is substantially complete (i.e., at the end of the active cycle), while the other equilibrate signal is turned off by the start of the subsequent cycle. The pulsed equilibrate signal drives much larger internal capacitive loads, such as large equilibration devices, while the non-pulsed (i.e.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: A method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input. The data associated with the read cycle propagates asynchronously through the memory to produce data which is then input to the pipeline circuit. The apparatus includes steering circuitry with precise timing for steering the data produced in the read cycle into an asserted one of several branches of a register. Selection circuitry is used to select for output the data which has been stored in the asserted branch upon receipt of a subsequent clock. The subsequent clock is one which occurs a programmable number of clocks after the first clock.

Abstract: A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

Abstract: A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

Abstract: Tri-port memory buffers having fast fall-through capability contain a custom tri-port memory array of moderate capacity having nonlinear columns of tri-port cells therein which collectively form four separate registers, and a substantially larger capacity supplemental memory array (e.g., DRAM array) having cells therein with reduced unit cell size. In particular, a preferred tri-port memory array is provided having a read port, a write port and a bidirectional input/output port. The tri-port memory array communicates internally with the supplemental memory array via the bidirectional input/output port and communicates with external devices (e.g., peripheral devices) via the read and write data ports.

Abstract: Accessing of adjacent arrays of memory in a semiconductor integrated circuit is facilitated by numbering the arrays of memory in accordance with a digital Gray code in which the addresses of adjacent arrays differ in only one digit. Each array is selected by the full array select address field. Each sense amplifier and I/O circuitry between memory arrays and shared by two adjacent memory arrays is selected by the full array select address field less one bit, that bit being the single address bit that differs between the addresses of the two adjacent Grey code numbered memory arrays. This permits faster decoding and enabling of the sense amplifier and I/O signal circuitry.