Patents by Inventor Robert J. Strain

Robert J. Strain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4728998
    Abstract: The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.
    Type: Grant
    Filed: July 30, 1986
    Date of Patent: March 1, 1988
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Robert J. Strain
  • Patent number: 4603471
    Abstract: The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.
    Type: Grant
    Filed: September 6, 1984
    Date of Patent: August 5, 1986
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Robert J. Strain
  • Patent number: 4585299
    Abstract: Optical wave-guiding components and a process for fabricating such components in a substrate using conventional integrated circuit fabrication techniques. Ions of a suitable dopant are selectively implanted in a silicon substrate to create an interior region defining a wave-guiding region of a first index of refraction. A wave confining region surrounding the wave-guiding region is created by oxidizing the silicon substrate. The wave confining region has a index of refraction lower than that of the interior wave-guiding region defined by the implanted dopant. Various configurations of components, from which various optical component characteristics can be obtained, are disclosed. The optical components also may be combined with electronic circuit components formed on the same silicon substrate.
    Type: Grant
    Filed: July 19, 1983
    Date of Patent: April 29, 1986
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Robert J. Strain
  • Patent number: 4559696
    Abstract: The suppression of the reverse injection of the carriers in a bipolar transistor, without adversely effecting forward injection, is carried out by modifying the energy gap characteristics of the transistor so that a greater barrier to reverse injection is presented than that which is confronted by the forward injected carriers. The energy gap of the emitter is increased, relative to that of the base, through ion implantation. The ions which are implanted are such that the resulting compound material has a higher energy gap than that of silicon into which they are implanted to selectively modify the emitter region so as to locally increase its energy gap. Preferred materials include carbon and nitrogen.
    Type: Grant
    Filed: July 11, 1984
    Date of Patent: December 24, 1985
    Assignee: Fairchild Camera & Instrument Corporation
    Inventors: Kranti Anand, Robert J. Strain
  • Patent number: 4480199
    Abstract: A circuit for providing an identification signal indicative of whether or not an integrated circuit has been repaired includes a circuit which operates at potentials outside the normal range of the integrated circuit. The circuit includes at least one transistor T1 serially connected between a TTL pin 10 of the integrated circuit and a fuse F1. The fuse F1 is also connected to a potential source V.sub.CC. If the integrated circuit is repaired the fuse F1 is opened, and consequently, application of a potential outside the normal range will cause current to flow if fuse F1 has not been opened, and cause no current to flow if fuse F1 has been opened.
    Type: Grant
    Filed: March 19, 1982
    Date of Patent: October 30, 1984
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: Ramesh C. Varshney, Robert J. Strain
  • Patent number: 4347656
    Abstract: A Charge Coupled Device (CCD) structure employing two levels of electrode metallization. The field plate electrodes are arranged in pairs with the second one of each pair partially overlapping and insulated from the first one of its pair and the first one of the next pair. The structure can be operated two-phase or four-phase with four electrodes per bit and three-phase with three electrodes per bit by providing suitable amounts of electrode overlap and suitable drive circuitry. A particularly advantageous mode of two-phase operation with four electrodes per bit is enabled by providing asymmetrical overlapping of electrodes, the second electrode of each pair overlapping the first electrode of its pair more than the first electrode of the next pair.
    Type: Grant
    Filed: December 22, 1980
    Date of Patent: September 7, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: George E. Smith, Robert J. Strain