Abstract: A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.

Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.

Abstract: A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.

Abstract: A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a first semiconductor stringer comprising a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and forming a gate above the superlattice.

Abstract: A semiconductor device may include a semiconductor substrate and first and second spaced apart shallow trench isolation (STI) regions therein, and a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first semiconductor stringer including a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and a gate above the superlattice.

Abstract: A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate including a respective plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include epitaxially forming a semiconductor layer on the superlattice, and annealing the superlattice to form a buried insulating layer in which the at least some semiconductor atoms are no longer chemically bound together through the at least one non-semiconductor monolayer therebetween.

Abstract: A process and system for treating wastewater is described. The invention degrades sludge produced by treatment of the wastewater to reduce or eliminate the need for sludge dewatering and disposal. The invention also reduces the amount of nutrient additives required to sustain the aerobic wastewater treatment process. In one embodiment the invention includes the steps of (a) providing an aerobic treatment system receiving a supply of the wastewater; (b) treating a supply of the sludge to rupture microbial cells present therein to produce treated sludge having an increased liquid:solid ratio and an increased degradation potential in comparison to untreated sludge; (c) conveying a supply of the treated sludge to the aerobic treatment system; and (d) substantially degrading the supply of treated sludge in the aerobic treatment system. The treated sludge may optionally be subjected to anaerobic digestion prior to delivery to the aerobic treatment system.

Abstract: A method for processing a semiconductor wafer in a single wafer processing chamber may include heating the single wafer processing chamber to a temperature in a range of 650-700° C., and forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Depositing the oxygen may include depositing the oxygen using an N2O gas flow.

Abstract: A method and device for treating spent wash water produced in operations such as heavy truck washing that includes hydraulic classification to remove fine sand and smaller particles from water such that up flow velocity of water plus solids in the classifier cause particulate solids to be retained in the classifier which promotes their agglomeration into larger particle sizes for easier subsequent removal for dewatering and disposal.

Abstract: A method for processing a semiconductor wafer in a single wafer processing chamber may include heating the single wafer processing chamber to a temperature in a range of 650-700° C., and forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Depositing the oxygen may include depositing the oxygen using an N2O gas flow.

Abstract: A process and system for treating wastewater is described. The invention degrades sludge produced by treatment of the wastewater to reduce or eliminate the need for sludge dewatering and disposal. The invention also reduces the amount of nutrient additives required to sustain the aerobic wastewater treatment process. In one embodiment the invention includes the steps of (a) providing an aerobic treatment system receiving a supply of the wastewater; (b) treating a supply of the sludge to rupture microbial cells present therein to produce treated sludge having an increased liquid:solid ratio and an increased degradation potential in comparison to untreated sludge; (c) conveying a supply of the treated sludge to the aerobic treatment system; and (d) substantially degrading the supply of treated sludge in the aerobic treatment system. The treated sludge may optionally be subjected to anaerobic digestion prior to delivery to the aerobic treatment system.

Abstract: A process and system for treating wastewater is described. The invention degrades sludge produced by treatment of the wastewater to reduce or eliminate the need for sludge dewatering and disposal. The invention also reduces the amount of nutrient additives required to sustain the aerobic wastewater treatment process. In one embodiment the invention includes the steps of (a) providing an aerobic treatment system receiving a supply of the wastewater; (b) treating a supply of the sludge to rupture microbial cells present therein to produce treated sludge having an increased liquid:solid ratio and an increased degradation potential in comparison to untreated sludge; (c) conveying a supply of the treated sludge to the aerobic treatment system; and (d) substantially degrading the supply of treated sludge in the aerobic treatment system. The treated sludge may optionally be subjected to anaerobic digestion prior to delivery to the aerobic treatment system.

Abstract: A process and system for treating wastewater is described. The invention degrades sludge produced by treatment of the wastewater to reduce or eliminate the need for sludge dewatering and disposal. The invention also reduces the amount of nutrient additives required to sustain the aerobic wastewater treatment process. In one embodiment the invention includes the steps of (a) providing an aerobic treatment system receiving a supply of the wastewater; (b) treating a supply of the sludge to rupture microbial cells present therein to produce treated sludge having an increased liquid:solid ratio and an increased degradation potential in comparison to untreated sludge; (c) conveying a supply of the treated sludge to the aerobic treatment system; and (d) substantially degrading the supply of treated sludge in the aerobic treatment system. The treated sludge may optionally be subjected to anaerobic digestion prior to delivery to the aerobic treatment system.

Abstract: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

Abstract: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

Abstract: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

Abstract: A method for making a multiple-wavelength opto-electronic device which may include providing a substrates and forming a plurality of active optical devices to be carried by the substrate and operating at different respective wavelengths. Moreover, each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

Abstract: A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof.

Abstract: A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The device may also include a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. The superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.

Abstract: A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. More particularly, the superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. Furthermore, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.