Abstract: A spacer-connector stud comprises a stacked array of glass epoxy laminates, each laminate having a copper layer laminated thereto. The top and bottom laminates of the stud include a spatial array of thermal contacts suitable as a footprint for C4 bump technology. A location is selected on a circuitized base card to accommodate the laminated stud. The stud has a thickness greater than twice the thickness of the components attached to the card. The thermal contacts on the stud, typically solderable, join to a wiring array on the card. A second multi-chip module card having attached and interconnected components on both sides of the second card is mechanically aligned with the based card and pressed against the contacts on the top layer of the stud to form an assembly. The assembly is heated causing the second card to become soldered to the contact footprint on the stud.

Abstract: In one aspect, circuitry for a digital logic function includes a first pair of input nodes for receiving respective first and second input signals, a second pair of input nodes for receiving respective complements of the first and second input signals, and an output node. The circuitry has a plurality of PFET-NFET pass gates. Such a pass gate has a first conducting electrode of the pass gate PFET connected to a first conducting electrode of the pass gate NFET, providing a first conducting node of the pass gate, and a second conducting electrode of the pass gate PFET connected to a second conducting electrode of the pass gate NFET, providing a second conducting node of the pass gate. The input nodes are connected to first conducting nodes of respective ones of the plurality of pass gates, and the second conducting nodes of the plurality of pass gates are connected to the circuitry output node.

Abstract: A spacer-connector stud comprises a stacked array of glass epoxy laminates, each laminate having a copper layer laminated thereto. The top and bottom laminates of the stud include a spatial array of thermal contacts suitable as a footprint for C4 bump technology. A location is selected on a circuitized base card to accommodate the laminated stud. The stud has a thickness greater than twice the thickness of the components attached to the card. The thermal contacts on the stud, typically solderable, join to a wiring array on the card. A second multi-chip module card having attached and interconnected components on both sides of the second card is mechanically aligned with the based card and pressed against the contacts on the top layer of the stud to form an assembly. The assembly is heated causing the second card to become soldered to the contact footprint on the stud.

Abstract: A spacer-connector stud comprises a stacked array of glass epoxy laminates, each laminate having a copper layer laminated thereto. The top and bottom laminates of the stud include a spatial array of thermal contacts suitable as a footprint for C4 bump technology. A location is selected on a circuitized base card to accommodate the laminated stud. The stud has a thickness greater than twice the thickness of the components attached to the card. The thermal contacts on the stud, typically solderable, join to a wiring array on the card. A second multi-chip module card having attached and interconnected components on both sides of the second card is mechanically aligned with the based card and pressed against the contacts on the top layer of the stud to form an assembly. The assembly is heated causing the second card to become soldered to the contact footprint on the stud.

Abstract: A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.

Abstract: A method and system for designing electronic devices by encouraging reuse as a design principle and rewarding both the design of reusable components as well as the subsequent reuse of such components. Typically, a design team evaluates each component in a proposed device for its potential to be implemented with a previously designed component. If a decision is made to forego previously designed components, the design team is encouraged to incorporate re-usability principles into the component design by a reward or compensation structure that rewards both the individual members of a team as well as the corporate entity to which the design team is assigned. The reward structure also encourages teams to use existing designs wherever possible by rewarding a team that reuses an existing component. An innovation administrator may adjust the relative rewards for incorporating reusability into a design vs. reusing a design to effect a preference for innovation in selected areas.

Abstract: A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.

Abstract: An electronic package which includes a circuitized substrate with a cavity and a first semiconductor chip positioned therein. The first chip is electrically coupled to conductive members located on the circuitized substrate. A second semiconductor chip is positioned on and electrically coupled to the first chip.

Abstract: An electronic package which includes a circuitized substrate with a cavity and a first semiconductor chip positioned therein. The first chip is electrically coupled to conductive members located on the circuitized substrate. A second semiconductor chip is positioned on and electrically coupled to the first chip.

Abstract: A portable computing device includes a processing unit coupled with a keyboard, a recording medium, and a display. The keyboard and the recording medium form portions of a support structure of the device and are generally directed in different directions. The recording medium is configured to receive input from a stylus operated by a user. The display is movable (e.g., pivotable and/or translatable) about the support structure to selectively suit use of the display in conjunction with the keyboard or use of the display in conjunction with the stylus and the recording medium. An elongatable arm can serve to connect the display with the support structure.

Abstract: An apparatus and method for transparent on-the-fly decompression of the program instruction stream of a processor. Connected between a processor and a memory storing compressed information is a decompression device. The decompression device, receives a request from the processor for information, retrieves compressed information from the memory, decompresses the retrieved compressed information to form uncompressed information, and transmits the uncompressed information to the processor. The compressed information may include both program instructions and data. When the decompression device receives a request for information, which includes an unmodified address, from the processor, it generates an index offset from the received unmodified address. An indexed address corresponding to the generated index offset is retrieved from an index table. Compressed information corresponding to the selected indexed address is retrieved from the memory and transmitted to the processor.

Abstract: A method for compressing a set of microcode to be utilized within a data processing system is disclosed. In accordance with the method and system of the present invention, a set of compiled microcode is parsed into multiple microcode segments, wherein each of these microcode segments is of equal length. Each of the microcode segments is then individually compressed by utilizing a data-compression routine. Next, all of these compressed microcode segments are concatenated to yield a set of compressed executable microcode. Finally, the starting address for each of the compressed microcode segments is stored in an indexer. By so doing, the required memory for storing the compressed executable microcode is reduced.