Abstract: Provided are a method for etching a phase change material of a phase change memory device and a semiconductor device formed according to the method. A temperature of the phase change memory device is lowered to a target temperature. A plasma etching process is applied to pattern the phase change material in response to cooling the temperature of the phase change memory device to the target temperature.

Abstract: Embodiments of include a technique for trimming an intermediate carbon layer by hydrogen (H2) plasma to achieve nanometer scale critical dimension patterning with high selectivity to metals and dielectrics. The technique includes providing a structure as a stack having at least one metal layer, a carbon layer, and at least one phase change material layer, the stack extending in a first dimension. The technique includes etching the carbon layer to a first width in a second dimension, the second dimension being perpendicular to the first dimension. The technique includes applying hydrogen plasma to laterally etch the carbon layer to a second width in the second dimension, the hydrogen plasma being applied with substantially no bias power and to avoid etching the at least one metal layer and the at least one phase change material layer.

Abstract: Provided are devices and methods relating to forming an electronic device, including providing a ruthenium (Ru) layer on a device layer. An organic planarization layer is formed on the Ru layer, wherein the Ru layer is positioned between the device layer and the organic planarization layer. One or more etching operations are performed to etch part of the organic planarization layer to form a remaining portion of the organic planarization layer and to etch part of the Ru layer to form a remaining portion of the Ru layer, wherein the etching operation to etch part of the Ru layer further includes forming a coating including Ru from the Ru layer on a sidewall of the remaining portion of the organic planarization layer.

Abstract: A semiconductor structure includes a first plurality of slanted features within a first region of a substrate. Two or more magnetic guiding structures are embedded within the first region of the substrate. The first plurality of slanted features is located between the two or more magnetic guiding structures for varying a magnetic field strength around the first plurality of slanted features. A second plurality of slanted features are located within a second region of the substrate. The second region of the substrate is adjacent to the first region of the substrate. The second plurality of slanted features include a second orientation angle that is different from a first orientation angle of the first plurality of slanted features.

Abstract: A semiconductor structure includes a first plurality of mandrel structures extending outwardly from a substrate. Each of the first plurality of mandrel structures includes a first side at a first inclination angle with respect to a surface plane of the substrate and a second side at a second inclination angle with respect to the surface plane of the substrate. A second plurality of mandrel structures extend outwardly from the substrate. Each of the second plurality of mandrel structures include a third side at a third inclination angle with respect to the surface plane of the substrate and a fourth side at a fourth inclination angle with respect to the surface plane of the substrate. A template structure for an imprint mask is formed by the first plurality of mandrel structures and the second plurality of mandrel structures.

Abstract: Provide an initial structure including a bottom electrode layer, a phase change material layer outward of the bottom electrode, a top electrode layer outward of the phase change material layer, and a patterned hard mask outward of the phase change material layer. Etch the initial structure using a first halogen plasma etchant at high wafer temperature to partially remove portions of the top electrode layer not protected by the patterned hard mask to produce an intermediate structure. Etch the intermediate structure using a second halogen plasma etchant at low wafer temperature to remove a remaining portion of the top electrode layer down to the phase change material layer, leaving a web of top electrode layer material under the patterned hard mask. Etch portions of the phase change material layer not protected by the web of top electrode layer material down to the bottom electrode layer, and remove the patterned mask.

Abstract: A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

Abstract: Provide an initial structure comprising a substrate, a hard mask outward of the substrate, a sacrificial organic layer outward of the hard mask, an anti-reflective coating outward of the sacrificial organic layer, and a patterned photoresist outward of the anti-reflective coating. Etch the initial structure to remove portions of the sacrificial organic layer and the anti-reflective coating not protected by the patterned photoresist down to the hard mask, to form sacrificial organic layer pillars under the patterned photoresist. Trim a critical dimension (CD) of the sacrificial organic layer pillars by etching with a gas that is selective to the anti-reflective coating and the hard mask, to trim sidewalls of the sacrificial organic layer pillars.

Abstract: An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.

Abstract: A process of improving a profile and repairing sidewall damage for phase change memory devices. The process includes applying inert ion beam etching to trim a sidewall of a layer of phase change memory material in a phase change memory device, where the sidewall has been damaged in reactive ion etching using halogens. In the process, the inert ion beam etching is with low energy. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined low temperature. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined small angle between an inert ion beam and a surface tangent of the sidewall.

Abstract: Embodiments of include a technique for trimming an intermediate carbon layer by hydrogen (H2) plasma to achieve nanometer scale critical dimension patterning with high selectivity to metals and dielectrics. The technique includes providing a structure as a stack having at least one metal layer, a carbon layer, and at least one phase change material layer, the stack extending in a first dimension. The technique includes etching the carbon layer to a first width in a second dimension, the second dimension being perpendicular to the first dimension. The technique includes applying hydrogen plasma to laterally etch the carbon layer to a second width in the second dimension, the hydrogen plasma being applied with substantially no bias power and to avoid etching the at least one metal layer and the at least one phase change material layer.

Abstract: A semiconductor structure includes a first plurality of slanted features within a first region of a substrate. Two or more magnetic guiding structures are embedded within the first region of the substrate. The first plurality of slanted features is located between the two or more magnetic guiding structures for varying a magnetic field strength around the first plurality of slanted features. A second plurality of slanted features are located within a second region of the substrate. The second region of the substrate is adjacent to the first region of the substrate. The second plurality of slanted features include a second orientation angle that is different from a first orientation angle of the first plurality of slanted features.

Abstract: A semiconductor structure includes a plurality of mandrel structures disposed above and in contact with a substrate. Each of the plurality of mandrel structures extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees. A template structure for an imprint mask is formed by the plurality of mandrel structures. The semiconductor structure further includes a layer of a conformal dielectric material covering the plurality of mandrel structures for providing stability and uniformity to the plurality of mandrel structures.

Abstract: An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.

Abstract: A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Abstract: Techniques for improving switching properties of phase change memory devices by boron surface passivation of the phase change memory material are provided. In one aspect, a phase change memory device includes: one or more phase change memory cells, each having a phase change material between a bottom electrode and a top electrode; and a boron-containing and nitrogen-containing bilayer on sidewalls of the phase change material to protect the phase change material from exposure to oxygen. An ovonic threshold switch can be implemented between the bottom electrode and the top electrode, in series with the phase change material. A method of fabricating the present phase change memory devices is also provided.

Abstract: Techniques for sidewall passivation and removal of redeposited materials and processing damage from phase change memory materials are provided. In one aspect, a phase change memory device includes: one or more phase change memory cells, where each of the phase change memory cells includes a phase change material between a bottom electrode and a top electrode; and a carbon and oxygen-containing passivation layer on sidewalls of the phase change material. An ovonic threshold switch can also be present between the bottom and top electrodes, in series with the phase change material, and the carbon and oxygen-containing passivation layer can also be present on sidewalls of the ovonic threshold switch. A method of fabricating the present phase change memory devices is also provided.

Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.