Abstract: A mushroom type phase change memory (PCM) cell includes a projection liner located between a PCM volume and a bottom electrode. The projection liner has been retained from a layer previously utilized as an etch stop layer during the fabrication of PCM cell and/or the fabrication of the higher level IC device. The projection liner may extend beyond the PCM sidewall(s) or side boundary. This section of the projection liner may be located or buried under a dielectric or an encapsulation spacer and may increase thickness uniformity of the projection liner below the PCM volume.

Abstract: A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.

Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

Abstract: A microfluidic chip with a high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

Abstract: A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Abstract: A cross-point memory array and stacked memory array structure. The memory array includes a plurality of first conductive line structures formed in a dielectric material layer; a plurality of memory elements, each memory element including a fill-in phase change memory (PCM) cell, and an access device enabling read or write access to said memory PCM structure; a plurality of second conductive line structures, the plurality of second conductive structures perpendicularly oriented relative to the plurality of first conductive structures. An individual memory element of the plurality of memory elements is conductively connected at a respective intersection between a first conductive line structure and a second conductive line structure. Each phase change memory (PCM) cell of a memory element at an intersection having a sub-lithographic conductive tuning liner disposed on only one sidewall of the PCM cell. The manufacturing maintains a minimal number of masking and processing steps.

Abstract: A voltage sensitive switching device has a first electrode, a second electrode, and a switching layer between the first and second electrodes. An in situ barrier layer is disposed between the first and second electrodes. The barrier layer comprises a composition including silicon and carbon. The switching device can be used in memory devices, including 3D cross-point memory.

Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: The present invention relates generally to the field of microelectronics, and more particularly to a structure and method of forming a biosensor having a nucleotide attracting surface tailored to reduce false detection of nucleotides and enabling optical detection of nucleotides. The biosensor may include an analyte-affinity layer on an upper surface of a dielectric layer. The analyte-affinity layer may include a plurality of cylindrical gold portions with dimensions tailored for a target analyte. A distance between adjacent portions of the plurality of portions may range from approximately 50% of a length of a target analyte to approximately 300% of a length of a target analyte. The plurality of portions of the analyte-affinity layer have an upper surface with a diameter ranging from approximately 3 nm to approximately 20 nm.

Abstract: The present invention relates generally to the field of microelectronics, and more particularly to a structure and method of forming a biosensor having a nucleotide attracting surface formed to reduce false detection of nucleotides and enabling electrical detection of nucleotides. The biosensor may include an analyte-affinity layer on an upper surface of a substrate. A conductive layer may extend a length of the substrate below and in contact with the analyte-affinity layer. The conductive layer may be electrically connected to one or more transistors. The analyte-affinity layer may have dimensions tailored for a target analyte. A distance between a first analyte-affinity layer and a second analyte-affinity layer may range from approximately 50% of a length of a target analyte to approximately 300% of a length of a target analyte. The analyte-affinity layer may have an upper surface with a diameter ranging from approximately 3 nm to approximately 20 nm.

Abstract: A cross-point memory array and method for manufacturing. The memory array includes a plurality of first conductive line structures formed in a dielectric material layer; a plurality of memory elements, each memory element including a fill-in phase change memory (PCM) cell, and an access device enabling read or write access to said memory PCM structure; a plurality of second conductive line structures, the plurality of second conductive structures perpendicularly oriented relative to the plurality of first conductive structures. An individual memory element of the plurality of memory elements is conductively connected at a respective intersection between a first conductive line structure and a second conductive line structure. Each phase change memory (PCM) cell of a memory element at an intersection having a sub-lithographic conductive tuning liner disposed on only one sidewall of the PCM cell. The manufacturing maintains a minimal number of masking and processing steps.

Abstract: A method, computer program product, and system for identifying a surface area size of a biosensing structure, for use in a bionsensor device, based on a plurality of nucleotides structures under test. A first set of properties are determined comprising: reaction coordinate values, and potential of mean force (PMF) values, for the plurality of nucleotide structures based on a first set of testing conditions comprising a first surface area material, a first surface area pattern, and a first surface area size. A second set of properties is determined comprising reaction coordinate values, and PMF values, for the plurality of nucleotide structures based on a second set of testing conditions comprising a second surface area material, a second surface area pattern, a second surface area size, or a combination thereof and a target population of nucleotide structures among the plurality of nucleotide structures are identified.

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.