Abstract: A disk drive is disclosed that utilizes multi-tiered solid state memory for caching data received from a host. Data can be stored in a memory tier that can provide the required performance at a low cost. For example, multi-level cell (MLC) memory can be used to store data that is frequently read but infrequently written. As another example, single-level cell (SLC) memory can be used to store data that is frequently written. Improved performance, reduced costs, and improved power consumption can thereby be attained.

Abstract: A disk drive is disclosed that varies its data redundancy policy for caching data in non-volatile solid-state memory as the memory degrades. As the non-volatile memory degrades, the redundancy of data stored in the non-volatile memory can be increased to counteract the effects of such degradation. Redundant data can be used to recover data stored in the non-volatile memory in case of a data corruption. Performance improvements and reduced costs of disk drives can thereby be attained.

Abstract: Migration of data in a data storage device (DSD). A spindle motor of the DSD is controlled to rotate a disk of the DSD to perform at least one operation on the disk and an operational activity level is determined for performing the at least one operation. It is determined whether the operational activity level is greater than a target level, and if it is determined that the operational activity level is not greater than the target level, data is transferred between a solid state memory of the DSD and the disk while the disk rotates.

Abstract: Disclosed herein is an architecture that pairs a controller with a NVM (non-volatile memory) storage system. The NVM storage system includes a bridge device that communicates with the controller. In one embodiment, the bridge device allows for certain data locations (blocks, pages or units at any other granularity) in the flash dies to be (1) placed into a reserved mode where data access is prevented (2) assigned into an SLC (Single-Level Cell) mode or an MLC (Multi-Level Cell) mode in response to controller command, (3) made available for data access after the assignment of mode. This flexibility enables the controller to increase SLC mode or MLC mode data locations based on run-time conditions. In one embodiment, the assignment of the reserved data locations is performed in a way to ensure that warranty conditions imposed by the memory vendors are observed.

Abstract: A flash memory device is disclosed comprising a flash controller for accessing a first flash memory over a first channel and a second flash memory over a second channel. A multi-command descriptor block is received from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request. A first group of the access commands are selected to execute concurrently and a second group of the access commands are selected to execute concurrently. The first group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. The second group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently.

Abstract: A non-volatile storage system is disclosed which provides a mapping table which includes a granularity which does not correspond to the page size of a non-volatile storage array. A reduced mapping table granularity enables more than one mapping entry to exist in a single page on the solid-state array. A write command which does not exceed a mapping table entry can invalidate only a portion of the written page, and can be combined with a second write command to write a new page of the solid-state array.

Abstract: Systems and methods for compression, formatting, and migration of data for data storage systems are disclosed. In some embodiments, data repacking can be used in any situation where embedded metadata needs to be accessed, such as during data migration, and where the underlying data is encrypted. In some embodiments, performance is increased because encrypted data is repacked without first performing decryption. In addition, data may also be compressed and repacking can be performed without performing decompression. Advantageously, there is no need to retrieve or wait for the availability of encryption key (or keys) or expand resources in decrypting (and decompressing) data before repacking it and encrypting repacked data. Available capacity for storing user data, reliability, and performance of the data storage system can be increased.

Abstract: Embodiments of solid-state storage system are provided herein include data recovery mechanism to recover data upon detection of a read error (e.g., an uncorrectable ECC error) in a storage element such as a page. In various embodiments, the system is configured to determine optimal reference voltage value(s) by evaluating the reference voltage value(s) of page(s) that are related to the page where the failure occurred. The related page(a) may include a page that is paired with the initial page where the failure occurred (e.g., the paired pages reside in a common memory cell), or a neighboring page that is physically near the page where the initial page, and/or a paired page of the neighboring page. In another embodiment, the system is configured to perform a time-limited search function to attempt to determine optimal reference voltage values through an iterative process that adjusts voltage values in a progression to determine a set of values that can retrieve the data.

Abstract: Embodiments of the invention are directed to improving parity determination in a data redundancy scheme. In a block oriented storage system, where the storage element block size is an integer multiple of the block size used on the host interface, parity can be calculated on clean boundaries of the host block. However, this is not always the case and storage inefficiency occurs as a result. Embodiments of the invention optimize RAID parity calculation in a non-volatile solid state device by allowing the RAID stripe depth (also termed a “strip”) to be a non-integer multiple of the size of the individual storage element, i.e., the non-volatile memory program granularity. This enables efficient use of storage space where the host data size does not match the storage element size of the non-volatile memory while providing a straightforward way of handling parity generation and data recovery.

Abstract: Embodiments of compression and formatting of data for data storage systems are disclosed. In some embodiments, a data storage system can compress fixed sized data before storing it on a media and format obtained variable sized compressed data for storing on the media that typically has fixed size storage granularity. One or more modules compress the incoming host data and create an output stream of fixed sized storage units that contain compressed data. The storage units are stored on the media. Capacity, reliability, and performance are thereby increased.

Abstract: Embodiments of multiple stream compression and formatting of data for data storage systems are disclosed. In some embodiments, a data storage system can compress multiple streams of fixed sized host data before storing it on a media and format obtained variable sized compressed data for storing on the media that typically has fixed size storage granularity. One or more modules compress the incoming host data and create multiple output streams of fixed sized storage units that contain compressed data. The storage units are stored on the media. Capacity, reliability, and performance are thereby increased.

Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.

Abstract: A non-volatile storage subsystem regulates energy consumption by controlling or “throttling” the rate at which memory operations are performed. During relatively idle periods in which few or no memory operations are performed, energy allotments or “counts” are accumulated to reflect unused energy. These accumulated energy counts may then be effectively allocated for use during bursts or other periods of relatively heavy memory activity, such that the memory operations are performed at a relatively high rate without causing a maximum average power consumption to be exceeded.

Abstract: Embodiments of the invention include systems and methods for reducing bus transfers for a storage device. In particular, these systems and methods reduce bus transfers by modifying an interface transfer protocol which designates the size of a multiple block read or write command is transmitted in a separate block transfer size command. Separate block transfer size commands can be omitted where the storage device maintains a record of a previously used block transfer size and reuses the size for subsequent multiple block read or write commands.

Abstract: Embodiments of the invention are directed to providing detailed error reporting of data operations performed on a NVM storage device. In one embodiment, a controller interfaces with a NVM storage device including NVM storage coupled with a bridge. In one embodiment, the controller is provided physical, page-level access to the NVM via the bridge, and the bridge provides detailed error reporting of the data operations that the bridge performs on the NVM on behalf of the controller. For example, the bridge may provide page level reporting indicating which page(s) failed during a read operation. Detailed error reporting allows the controller to better understand the failures that occurred in a data access operation in the NVM. It also enables the controller to manage the flash media at the physical page/block level. In one embodiment, detailed error reporting also enables the return of discontinuous ranges of data with the error portions removed.

Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.

Abstract: A storage subsystem implements a background process for selecting voltage reference values to use for reading data from a non-volatile memory array, such as an array of multi-level cell (MLC) flash memory. The process involves performing background read operations using specific sets of voltage reference values while monitoring the resulting bit error counts. The selected voltage reference values for specific pages or other blocks of the array are stored in a table. Read operations requested by a host system are executed using the corresponding voltage reference values specified by the table.

Abstract: Embodiments of the invention are directed to systems and methods for reducing an amount of backup power needed to provide power fail safe preservation of a data redundancy scheme such as RAID that is implemented in solid state storage devices where new write data is accumulated and written along with parity data. Because new write data cannot be guaranteed to arrive in integer multiples of stripe size, a full stripe's worth of new write data may not exist when power is lost. Various embodiments use truncated RAID stripes (fewer storage elements per stripe) to save cached write data when a power failure occurs. This approach allows the system to maintain RAID parity data protection in a power fail cache flush case even though a full stripe of write data may not exist, thereby reducing the amount of backup power needed to maintain parity protection in the event of power loss.

Abstract: Redundant “parity” RAID (5, 6, 50, 60) is a well-known technique for increasing data reliability beyond the failure rate of an individual storage device. In many implementations of redundant RAID, when a storage element is lost, a replacement or spare element is required to restore redundancy. A typical solid state storage device is over-provisioned with more storage media than is required to satisfy the specified user capacity. Embodiments of the present invention utilize the additional over-provisioned capacity and potentially modify the stripe size to restore RAID redundancy when a storage element or path (i.e., page, block, plane, die, channel, etc.) has failed. In some cases, this may also involve reducing the RAID stripe size.

Abstract: Embodiments of the present invention use high granularity reliability information (e.g., from individual pages, blocks, etc.) in a solid state storage device to vary the number of elements in each RAID stripe and to combine the elements in a stripe to achieve a more homogenous reliability metric across the device. In one embodiment, a reliability metric of a stripe group of storage elements is calculated based on monitored conditions of the storage elements such as erase counts, number of bit errors encountered, calculated voltage reference values, etc. The reliability metrics of the stripe groups are used to decide how many storage elements and which storage elements should be combined in the redundant RAID stripes to achieve a desired probability of data loss for the overall device. The target error probability could be fixed for the life of the storage device or adjusted as the device wide error rates increase.