Patents by Inventor Robert L. Pitts
Robert L. Pitts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11024620Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.Type: GrantFiled: August 2, 2018Date of Patent: June 1, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Thomas J. Aton, Roger Mark Terry, Robert L. Pitts
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Patent number: 10192859Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.Type: GrantFiled: April 24, 2012Date of Patent: January 29, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Thomas J. Aton, Roger Mark Terry, Robert L. Pitts
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Publication number: 20180342494Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.Type: ApplicationFiled: August 2, 2018Publication date: November 29, 2018Inventors: Thomas J. Aton, Roger Mark Terry, Robert L. Pitts
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Publication number: 20170018483Abstract: One example includes a conductive leadframe configured to couple to an integrated circuit (IC) chip die on a contact surface of the IC chip die. The conductive leadframe includes a plurality of chip-pin connections configured to facilitate conductive coupling to bond pads of the IC chip die via conductive lead wires. The conductive leadframe also includes a support beam that extends across the conductive leadframe along the contact surface of the IC chip die to enable support of the IC chip die to the conductive leadframe at a plurality of support locations during testing of the IC associated with the IC chip die.Type: ApplicationFiled: December 31, 2015Publication date: January 19, 2017Inventors: Robert L. Pitts, Leslie E. Stark
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Patent number: 8595656Abstract: A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.Type: GrantFiled: October 21, 2010Date of Patent: November 26, 2013Assignee: Texas Instruments IncorporatedInventors: Thomas J. Aton, Gregory C. Baldwin, Robert L. Pitts
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Patent number: 8344479Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: GrantFiled: February 15, 2011Date of Patent: January 1, 2013Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, Greg C. Baldwin
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Publication number: 20120286331Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at i least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.Type: ApplicationFiled: April 24, 2012Publication date: November 15, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Thomas J. Aton, Roger Mark Terry, Robert L. Pitts
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Publication number: 20120102441Abstract: A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.Type: ApplicationFiled: October 21, 2010Publication date: April 26, 2012Applicant: Texas Instruments IncorporatedInventors: Thomas J. Aton, Gregory C. Baldwin, Robert L. Pitts
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Patent number: 8093716Abstract: The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.Type: GrantFiled: July 29, 2005Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, Bryan Sheffield, Roger Griesmer, Joe McPherson
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Publication number: 20110216619Abstract: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.Type: ApplicationFiled: May 12, 2011Publication date: September 8, 2011Inventors: Hugh T. Mair, Robert L. Pitts, Alice Wang, Sumanth K. Gururjarao, Ramaprasath Vilangudipitchai, Gordon Gammie, Uming Ko
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Patent number: 7961546Abstract: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.Type: GrantFiled: October 27, 2008Date of Patent: June 14, 2011Assignee: Texas Instruments IncorporatedInventors: Hugh T. Mair, Robert L. Pitts, Alice Wang, Sumanth K. Gururjarao, Ramaprasath Vilangudipitchai, Gordon Gammie, Uming Ko
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Publication number: 20110133880Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: ApplicationFiled: February 15, 2011Publication date: June 9, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert L. Pitts, Greg C. Baldwin
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Patent number: 7888227Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: GrantFiled: June 12, 2008Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, Greg C. Baldwin
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Patent number: 7800409Abstract: A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height.Type: GrantFiled: July 30, 2007Date of Patent: September 21, 2010Assignee: Texas Instruments IncorporatedInventor: Robert L. Pitts
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Patent number: 7784015Abstract: Methods are disclosed for the layout and manufacture of microelectronic circuits. The methods employ the monitoring of the placement of macros within circuit layouts for design rule compliance. Upon detection of noncompliance, the macros associated with noncompliance are adapted to bring the layout within the design rules. In a preferred embodiment of the invention monitoring the relative positions of macros includes identifying instances of coinciding macro (x, y) coordinates. Adapting noncompliant macros further includes steps for maintaining minimum (x, y) distances between adjacent macro corners.Type: GrantFiled: July 5, 2005Date of Patent: August 24, 2010Assignee: Texas Instruments IncorporatedInventor: Robert L. Pitts
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Publication number: 20100103760Abstract: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.Type: ApplicationFiled: October 27, 2008Publication date: April 29, 2010Inventors: Hugh T. Mair, Robert L. Pitts, Alice Wang, Sumanth K. Gururjarao, Ramaprasath Vilangudipitchai, Gordon Gammie, Uming Ko
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Patent number: 7671663Abstract: The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.Type: GrantFiled: December 12, 2006Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: Theodore W. Houston, Michael P. Clinton, Robert L. Pitts
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Publication number: 20090160029Abstract: Disclosed is a semiconductor wafer with an array of integrated circuit chips with scribe lane structures forming edge and intra-chip seals for use in protecting the IC circuitry. Substantially parallel scribe seal structures extend around the periphery of each chip; the two scribe seal structures have a separation gap. Preferred embodiments of the invention also include wafers of ICs each having two or more distinctive circuitry blocks such as analog and digital circuitry, separated by an intra-chip seal. Preferred embodiments of also include ICs having two or more distinctive circuit blocks separated by a scribe seal structure with a separation gap and a routing channel for use in passing signals among the circuit blocks.Type: ApplicationFiled: February 27, 2009Publication date: June 25, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert L. Pitts, Thad E. Briggs, Srinivasan Venkatraman
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Publication number: 20090033368Abstract: A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height.Type: ApplicationFiled: July 30, 2007Publication date: February 5, 2009Applicant: Texas Instruments IncorporatedInventor: Robert L. Pitts
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Publication number: 20080286933Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: ApplicationFiled: June 12, 2008Publication date: November 20, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert L. Pitts, Greg C. Baldwin