Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

Abstract: The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.

Abstract: A reliability test chain includes: a stress chain; and transition time control circuits coupled to tap points along the stress chain such that transition times of a signal on the stress chain are controlled.

Abstract: According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay elements. Each delay element operates as a delay element through the use of one or more transistors of only a first type and no transistors of the opposite type. The method further includes operating the ring oscillator and measuring the frequency resulting from the ring oscillator over time. The magnitude of an isolated degradation mechanism is determined based on a comparison of the measured frequency and an expected frequency for the ring oscillator absent degradation.

Abstract: An integrated circuit (IC). The integrated circuit comprises an array (14) of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (40), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry (12) for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry (12) for reading selected ones of the data cells in a read mode.

Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

Abstract: An integrated circuit (IC). The integrated circuit comprises an array (14) of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (40), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry (12) for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry (12) for reading selected ones of the data cells in a read mode.

Abstract: This invention describes a means for preventing eFuses from growing back under successive programming pulses after being successfully fused by an earlier set of programming pulses. The solution is achieved through the use of an adaptive programming algorithm for blowing the eFuses. In the adaptive algorithm once a high enough resistance on a blown eFuse has been attained it will not receive additional programming pulses that could cause it to become measurably lower resistance.

Abstract: This invention describes a means for preventing eFuses from growing back under successive programming pulses after being successfully fused by an earlier set of programming pulses. The solution is achieved through the use of an adaptive programming algorithm for blowing the eFuses. In the adaptive algorithm once a high enough resistance on a blown eFuse has been attained it will not receive additional programming pulses that could cause it to become measurably lower resistance.

Abstract: In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more gates, and a word line for controlling the gates of the plurality of memory cells. A driver is coupled to the word line at a first location. The driver is operable to drive the gates of the memory cells. A load device is coupled to the word line at a second location remote from the first location. The load device is operable to pull a set of gates electrically isolated from the driver to a substantially non-floating state.

Abstract: An embodiment of the invention is circuitry that contains a fuse 9 connected between a decoupling capacitor 4 and a power rail 11. Another embodiment of the invention is a method of eliminating defective decoupling capacitors 4 by applying power to a power rail 10 to blow a fuse 9 that is connected to a defective decoupling capacitor 4.

Abstract: In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more gates, and a word line for controlling the gates of the plurality of memory cells. A driver is coupled to the word line at a first location. The driver is operable to drive the gates of the memory cells. A load device is coupled to the word line at a second location remote from the first location. The load device is operable to pull a set of gates electrically isolated from the driver to a substantially non-floating state.

Abstract: A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method comprising: storing a plurality of configuration data in the non-volatile memory and, providing power to the volatile memory. After providing power to the volatile memory, serially loading the configuration data into the registers of the volatile memory to configure the semiconductor device.

Abstract: A circuit (100) for protecting sensitive data stored in a storage area (108) includes a one time programmable device such as a fuse element (104) coupled to the input data path (102), and a one time programmable device such as fuse element (112) coupled to the output data path (118). Once sensitive data is loaded into the storage area (108), either one of, or both of the fuses (104, 112) can be activated (blown) in order to prevent access to the data stored in storage area (108). Optionally, a fuse element (130) can also be added to the internal circuit data line (120) that would prevent both internal and external access to the stored data.

Abstract: A method and system for minimizing bit stress in a non-volatile memory during an erase operation are disclosed, which can increase the absolute value of the gate voltage of a memory cell incrementally with each subsequent high voltage erase pulse during the erase operation, instead of ramping up the absolute value of the gate voltage completely during each pulse. Also, each high voltage pulse can be conditioned so that its leading edge does not transition too quickly. Furthermore, a state machine for a flash memory device is disclosed, which can perform, among other things, the erase functions and/or algorithms used for the flash memory.

Abstract: A memory having flexible column redundancy and flexible row redundancy plural column sticks, each column stick comprising a plurality of data lines. Positioned on either side of the memory are redundant column sticks each comprising a plurality of data lines. A column redundancy control identifies a faulty operating column stick in the memory and generates a column shift control signal to a column shift multiplexer that responds to the column shift control signal to substitute in the memory a redundant column stick for the identified faulty operating column stick. Similar redundant row sticks above and below the normal rows enable a row redundancy controller to signal a row shift multiplexer to replace a faulty operating row stick in the memory.

Abstract: A circuit (100) for protecting sensitive data stored in a storage area (108) includes a one time programmable device such as a fuse element (104) coupled to the input data path (102), and a one time programmable device such as fuse element (112) coupled to the output data path (118). Once sensitive data is loaded into the storage area (108), either one of, or both of the fuses (104, 112) can be activated (blown) in order to prevent access to the data stored in storage area (108). Optionally, a fuse element (130) can also be added to the internal circuit data line (120) that would prevent both internal and external access to the stored data.

Abstract: A more efficient memory access is provided by providing fast access to words on the same physical row (wordline) in memory whether sequential or not, by, after issuance of an address, the detection of whether the current access is on the same physical memory row as the previous access and accordingly allows a different number of wait states, dependent on whether the access is on the same row or not.

Abstract: A more efficient memory access is provided by providing fast access to words on the same physical row (wordline) in memory whether sequential or not, by, after issuance of an address, the detection of whether the current access is on the same physical memory row as the previous access and accordingly allows a different number of wait states, dependent on whether the access is on the same row or not.

Abstract: A memory having flexible column redundancy and flexible row redundancy comprises a multi-column stick configuration each column stick comprising a plurality of data lines. Further, the memory has a multi-row stick configuration, with each row stick comprising a plurality of data rows. Positioned on either side of the memory are redundant column sticks each comprising a plurality of data lines. Positioned above and below the memory are redundant row sticks, each comprising a plurality of data rows. A column redundancy control identifies a faulty operating column stick in the memory and generates a column shift control signal to a column shift multiplexer that responds to the column shift control signal to substitute in the memory a redundant column stick for the identified faulty operating column stick. Further, the memory comprises a row redundancy controller identifies a faulty operating row stick in the memory to generate a row shift control signal to a row shift multiplexer.