Patents by Inventor Robert L. Sankman

Robert L. Sankman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9971089
    Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Kemal Aygun, Robert L. Sankman
  • Patent number: 9941054
    Abstract: An embedded thin film capacitor and methods of its fabrication are disclosed. The embedded thin film capacitor includes two conductive plates separated by a dielectric layer. In embodiments, the capacitor is enclosed within a package substrate. A method of forming the embedded thin film capacitor includes forming a first insulating layer on a bottom plate and a first trace. A first opening is then formed in a first insulating layer to expose a first region of a bottom plate. An adhesive layer is then formed on the first insulating layer and on top of the exposed first region of the bottom plate. A second opening is formed through the insulating layer and the first insulating layer to expose a second region of the bottom plate. A top plate is formed within the first opening and a via is formed within the second opening.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Daniel N. Sobieski, Sri Ranga Sai Boyapati
  • Publication number: 20180096975
    Abstract: A high density package on package electrical device is disclosed. The electrical device comprises a first integrated circuit package comprising a substrate, an integrated circuit component attached to the substrate, and a molding compound covering the component, wherein the top of the molding compound has a redistribution layer of metal covering at least part of the molding compound. The device further comprises a second integrated circuit package including a second substrate, a semiconductor component attached to the substrate, and a molding compound covering the electronic component, wherein the bottom of the substrate includes metal contacts for communication between the second integrated circuit package and other components. The device further comprises a solder layer that connects the top of the first integrated circuit package to the bottom of the second electric package by connecting the metal of the redistribution layer to the metal connections on the bottom of the second substrate.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Fay Hua, Robert L. Sankman
  • Publication number: 20180090471
    Abstract: An apparatus is described that includes a package on package structure. The package on package structure includes an interposer to implement electrical interconnections between an upper package of the package on package structure and a lower package of the package on package structure. The interposer has packed wires, the packed wires have respective polygonal cross sections.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: Chia-Pin CHIU, Yoshihiro TOMITA, Yoko SEKIHARA, Robert L. SANKMAN
  • Patent number: 9927211
    Abstract: Described herein are technologies related to passive or active cloaking devices. More particularly, the passive or active cloaking devices utilize input/output grating couplers and waveguides to create an impression of invisibility on an object that is covered by the passive or active cloaking devices.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Ian A. Young, Johanna M. Swan, Robert L. Sankman, Marko Radosavljevic
  • Patent number: 9922916
    Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Sanka Ganesan, Zhiguo Qian, Robert L. Sankman, Krishna Srinivasan, Zhaohui Zhu
  • Publication number: 20180068926
    Abstract: Embodiments of the present disclosure describe an energy storage material for thermal management and associated techniques and configurations. In one embodiment, an energy storage material may include an organic matrix and a solid-solid phase change material dispersed in the organic matrix, the solid-solid phase change material to change crystalline structure and absorb heat while remaining a solid at a threshold temperature associated with operation of an integrated circuit (IC) die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 27, 2015
    Publication date: March 8, 2018
    Inventors: JAN KRAJNIAK, TANNAZ HARIRCHIAN, KELLY P. LOFGREEN, JAMES C. MATAYABAS, Jr., NACHIKET R. RARAVIKAR, ROBERT L. SANKMAN
  • Publication number: 20180033648
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Application
    Filed: October 5, 2017
    Publication date: February 1, 2018
    Inventors: Robert L Sankman, John S. Guzek
  • Patent number: 9865568
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Islam A. Salama, Ram S. Viswanath, Robert L. Sankman, Babak Sabi, Sri Chaitra Jyotsna Chavali
  • Publication number: 20180005928
    Abstract: Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Robert L. Sankman, Sanka Ganesan
  • Patent number: 9847234
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, John S. Guzek
  • Patent number: 9820384
    Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Sasha Oster, Robert L. Sankman, Charles Gealer, Omkar Karhade, John S. Guzek, Ravi V. Mahajan, James C. Matayabas, Jr., Johanna Swan, Feras Eid, Shawna Liff, Timothy McIntosh, Telesphor Kamgaing, Adel Elsherbini, Kemal Aygun
  • Patent number: 9807866
    Abstract: An electronic package having a substrate that includes signal traces and ground traces; an electronic component mounted on an upper surface of the substrate such that the electronic component is electrically connected to the signal traces and the ground traces in the substrate; an insulating layer covering the electronic component and the upper surface of the substrate; and an electromagnetic interference shielding mold covering the insulation layer such that the electromagnetic interference shielding mold is electrically connected to the ground traces in the substrate. In some forms of the electronic package, the electromagnetic interference shielding mold is electrically connected to the ground traces through openings in the insulation layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Adel Elsherbini, Robert L. Sankman, Kemal Aygun
  • Publication number: 20170309578
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Applicant: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Publication number: 20170299342
    Abstract: Described herein are technologies related to passive or active cloaking devices. More particularly, the passive or active cloaking devices utilize input/output grating couplers and waveguides to create an impression of invisibility on an object that is covered by the passive or active cloaking devices.
    Type: Application
    Filed: April 11, 2016
    Publication date: October 19, 2017
    Applicant: Intel Corporation
    Inventors: Ian A. Young, Johanna M. Swan, Robert L. Sankman, Marko Radosavljevic
  • Publication number: 20170288290
    Abstract: Electrical cable technology is disclosed. In one example, an electrical cable can include a transmission line conductor, a ground conductor, and a dielectric material. The dielectric material can have at least a portion with a thickness separating the transmission line conductor and the ground conductor that is variable along a length of the electrical cable. Such a non-uniform cable (e.g., a cable having components or features that vary in size and/or geometry along the length of the cable) can provide high IO density with acceptable conductive losses and cross-talk while maintaining a desired impedance.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Sasha N. Oster, Adel A. Elsherbini, Kemal Aygun, Robert L. Sankman
  • Publication number: 20170287847
    Abstract: Apparatus and methods are provided for an integrated circuit package that includes an integrated EMI shield. In an example, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on the bottom surface of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, a conductive film coupled to the conductive fence, the film located above a top surface of the integrated circuit and coextensive with a footprint defined by the conductive fence.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Rajendra C. Dias, Robert L. Sankman, Joshua D. Heppner, Mitul B. Modi, Yoshihiro Tomita
  • Publication number: 20170268971
    Abstract: Embodiments are generally directed to membrane test for mechanical testing of wearable devices. A mechanical testing system includes an actuation mechanism including a clamp to hold a membrane including stretchable electronics over an opening in the actuation mechanism, wherein the actuation mechanism is to apply pressure to the membrane through the opening; and a testing logic to control the application and release of pressure on the membrane by the actuation mechanism.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Ravindranth V. MAHAJAN, Rajendra C. DIAS, Pramod MALATKAR, Steven A. KLEIN, Vijay SUBRAMANIA, Aleksandar ALEKSOV, Robert L. SANKMAN
  • Publication number: 20170268972
    Abstract: Embodiments are generally directed to a lateral expansion apparatus for mechanical testing of stretchable electronics. An embodiment of a system includes a compressible cylinder to apply mechanical forces to a stretchable electronics device by the compression and release of the compressible cylinder; a compression unit to compress to the compressible cylinder, wherein the compression unit is to apply a compression force in a direction along an axis of the compressible cylinder to generate lateral expansion of the compressible cylinder; and a testing logic to control compression and release of the compressible cylinder.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Vijay Krishnan SUBRAMANIAN, Steven A. KLEIN, Rajendra C. DIAS, Pramod MALATKAR, Aleksandar ALEKSOV, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Publication number: 20170269017
    Abstract: Embodiments are generally directed to air bladder based mechanical testing for stretchable electronics. An embodiment of a system includes an inflatable bladder to apply mechanical force to a stretchable electronics device by the inflation and deflation of the inflatable bladder; a valve unit to control fluid pressure applied to the inflatable bladder; and a control unit to control inflation and deflation of the inflatable bladder.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Steven A. KLEIN, Rajendra C. DIAS, David C. MCCOY, Lars D. SKOGLUND, Vijay SUBRAMANIAN, Aleksander ALEKSOV, Pramod MALATKAR, Ravindranath V. MAHAJAN, Robert L. SANKMAN