Patents by Inventor Robert M. Duboc

Robert M. Duboc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6278066
    Abstract: A spacer (100 or 600/1000A/1000B) situated between a faceplate structure (301) and a backplate structure (302) of a flat panel display is configured to be self standing. In one implementation, a pair of spacer feet (111 or 113 and 112 or 114) are located over the same face surface, or over opposite face surfaces, of a spacer wall (101) near opposite ends of the wall. An edge electrode (121 or 122) is located over an edge surface of the spacer adjacent to the faceplate structure or the backplate structure. In another implementation, a spacer clip (1000A or 1000B) clamps opposite face surfaces of a spacer wall (600) largely at one end of the wall.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: August 21, 2001
    Assignee: Candescent Technologies Corporation
    Inventors: Theodore S. Fahlen, Alfred S. Conte, Robert M. Duboc, Jr., George B. Hopple, John K. O'Reilly, Vasil M. Chakarov, Robert L. Marion, Steve T. Cho, Robert G. Neimeyer, Jennifer Y. Sun, David L. Morris, Christopher J. Spindt, Kollengode S. Narayanan
  • Patent number: 6235179
    Abstract: An electroplated structure for a field emission display device and method for forming an electroplated structure for a field emission display device. In one embodiment, the present invention forms a molded structure over selected portions of a flat panel display device. Next, the present embodiment deposits an electroplating seed layer over the molded structure. After the deposition of the electroplating seed layer, the present embodiment electroplates material onto portions of the electroplating seed layer such that an electroplated structure is formed at desired regions of the flat panel display device. In such an embodiment, the present invention provides an electroplated structure which contains substantially no polyimide material. As a result, the present embodiment eliminates the cost and production of outgassed contaminants associated with prior art structures.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: May 22, 2001
    Assignee: Candescent Technologies Corporation
    Inventors: Ronald S. Besser, Robert M. Duboc, Jr.
  • Patent number: 6204596
    Abstract: An electron-emitting device contains a lower conductive region (22), a porous insulating layer (24A, 24B, 24D, 24E, or 24F) overlying the lower conductive region, and a multiplicity of electron-emissive elements (30, 30A, or 30B) situated in pores (281) extending through the porous layer. The pores are situated at locations substantially random relative to one another. The lower conductive region typically contains a highly conductive portion (22A) and an overlying highly resistive portion (22B). Alternatively or additionally, a patterned gate layer (34B, 40B, or 46B) overlies the porous layer. Openings (36, 42, or 541) corresponding to the filaments extend through the gate layer at locations generally centered on the filaments such that the filaments are separated from the gate layer.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: March 20, 2001
    Assignee: Candescent Technologies Corporation
    Inventors: John M. Macaulay, Peter C. Searson, Robert M. Duboc, Jr., Christopher J. Spindt
  • Patent number: 6147450
    Abstract: An apparatus for removing contaminants from a display device using an auxiliary chamber, and a method for attaching the auxiliary chamber to the display device. In one embodiment, an auxiliary chamber is adapted to be coupled to a surface of a display device. The auxiliary chamber is adapted to be coupled to the surface of the display device such that contaminants within the display device can travel from the display device into the auxiliary chamber. The auxiliary chamber further includes a getter which is disposed therein. The getter is adapted to capture the contaminants once the contaminants travel from the display device into the auxiliary chamber. In so doing, the present invention eliminates the need for getter material to be placed within the active area of the display device. As a result, the present invention increases the usable amount of space available within the display device. This extra space can then be utilized by features such as, for example, additional field emitters.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: November 14, 2000
    Assignee: Candescent Technologies Corporation
    Inventors: William C. Fritz, Igor L. Maslennikov, Robert M. Duboc, Jr., Theodore S. Fahlen, George B. Hopple
  • Patent number: 6022652
    Abstract: A method for creating a faceplate of a display provides a faceplate substrate with a faceplate interior side and a faceplate exterior side. A plurality of barriers are formed on the faceplate interior side, with the barriers defining a plurality of subpixel volumes. Phosphor containing photopolymerizable material mixtures of red, green and blue, are deposited into subpixel volumes, and create a faceplate interior side/phosphor interface. At least a portion of the phosphor containing photopolymerizable material mixture is exposed with sufficient actinic light through the faceplate interior side/phosphor interface to polymerize a selected depth of the phosphor containing photopolymerizable material mixture in the subpixel volumes, and form a polymerized phosphor containing material in a plurality of subpixel volumes. Non-polymerized phosphor containing photopolymerizable material is removed from the polymerized phosphor containing material.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: February 8, 2000
    Assignee: Candescent Technologies Corporation
    Inventors: Duane A. Haven, Paul M. Drumm, Robert M. Duboc, Jr.
  • Patent number: 5913704
    Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: June 22, 1999
    Assignee: Candescent Technologies Corporation
    Inventors: Christopher J. Spindt, John M. Macaulay, Robert M. Duboc, Jr., Peter C. Searson
  • Patent number: 5900301
    Abstract: Fabrication of an electron-emitting device entails distributing electron-emissive carbon-containing particles (22) over a non-insulating region (12). The particles can be made electron emissive after the particle distributing step. Particle bonding material (24) is typically provided to bond the particles to the non-insulating region. The particle bonding material can include carbide formed by heating or/and can be created by modifying a layer (32) provided between the non-insulating region and the particles. In one embodiment, the particles emit electrons primarily from graphite or/and amorphous carbon regions. In another embodiment, the particles are made electron-emissive prior to the particle distributing step.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: May 4, 1999
    Assignees: Candescent Technologies Corporation, Massachusetts Institute of Technology, Advanced Technology Materials, Inc.
    Inventors: George E. Brandes, Jonathan C. Twichell, Michael W. Geis, John M. Macaulay, Robert M. Duboc, Jr., Christopher J. Curtin
  • Patent number: 5851669
    Abstract: A field-emission structure suitable for large-area flat-panel televisions centers around an insulating porous layer that overlies a lower conductive region situated over insulating material of a supporting substrate. Electron-emissive filaments occupy pores extending through the porous layer. A conductive gate layer through which openings extend at locations centered on the filaments typically overlies the porous layer. Cavities are usually provided in the porous layer along its upper surface at locations likewise centered on the filaments.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: December 22, 1998
    Assignee: Candescent Technologies Corporation
    Inventors: John M. Macaulay, Peter C. Searson, Robert M. Duboc, Jr., Christopher J. Spindt
  • Patent number: 5827099
    Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: October 27, 1998
    Assignee: Candescent Technologies Corporation
    Inventors: Christopher J. Spindt, John M. Macaulay, Robert M. Duboc, Jr., Peter C. Searson
  • Patent number: 5798604
    Abstract: A flat panel display includes a cathode (302/303/304, 501, or 601a/601b), a conductive gate layer (306, 502, or 602a/602b) overlying the cathode, and a thicker patterned conductive further layer (307, 503, or 603) contacting the gate layer above the cathode. The cathode contains emitters exposed through a multiplicity of laterally separated sets of openings in the gate layer. Each set of gate openings is exposed through a corresponding one of a plurality of holes in the further layer. An anode overlies the gate and further layers.
    Type: Grant
    Filed: January 5, 1996
    Date of Patent: August 25, 1998
    Assignee: Candescent Technologies Corporation
    Inventors: Robert M. Duboc, Jr., Paul A. Lovoi
  • Patent number: 5725787
    Abstract: A light-emitting structure (306) contains a main section (302), a pattern of ridges (314) situated along the main section, and a plurality of light-emissive regions (313) situated in spaces between the ridges. The light-emissive regions produce light of various colors upon being hit by electrons. The ridges, which extend further away from the main section than the light-emissive regions, are substantially non-emissive of light when hit by electrons. Each ridge includes a dark region. The ridges thereby form a raised black matrix that improves contrast and color purity. When the light-emitting structure is used in an optical display, the raised black matrix contacts internal supports (308) and, in so doing, protects the light-emissive regions from being damaged. The light-emitting structure can be formed according to various techniques of the invention.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: March 10, 1998
    Assignee: Candescent Technologies Corporation
    Inventors: Christopher J. Curtin, Ronald S. Nowicki, Theodore S. Fahlen, Robert M. Duboc, Jr., Paul A. Lovoi
  • Patent number: 5667418
    Abstract: A flat panel device is provided with an internal support structure in the form of a spacer. In one fabrication technique, the spacer is formed as a laminate of multiple layers of ceramic, glass-ceramic, ceramic-reinforced glass, devitrified glass, or/and metal coated with electrically insulating material. The spacer is placed between a backplate structure and a faceplate structure which are connected together to form an enclosure that encases the spacer. In another fabrication technique, the spacer constitutes a spacer wall placed between the backplate and faceplate structures. When the backplate structure is connected to the faceplate structure to form an enclosure that encases the spacer wall, the spacer wall follows a corrugated path adjacent to at least one of the faceplate and backplate structures.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: September 16, 1997
    Assignee: Candescent Technologies Corporation
    Inventors: Theodore S. Fahlen, Robert M. Duboc, Jr., Paul A. Lovoi
  • Patent number: 5608283
    Abstract: In one electron-emitting device, non-insulating particle bonding material (24) securely bonds electron-emissive carbon-containing particles (22) to an underlying non-insulating region (12). The carbon in each carbon-containing particle is in the form of diamond, graphite, amorphous carbon, or/and silicon carbide. In another electron-emitting device, electron-emissive pillars (22/28) overlie a non-insulating region (12). Each pillar is formed with an electron-emissive particle (22) and an underlying non-insulating pedestal (28).
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: March 4, 1997
    Assignee: Candescent Technologies Corporation
    Inventors: Jonathan C. Twichell, George R. Brandes, Michael W. Geis, John M. Macaulay, Robert M. Duboc, Jr., Christopher J. Curtin
  • Patent number: 5589731
    Abstract: A flat panel device contains a faceplate, a backplate, a light-emitting mechanism, and a spacer. The faceplate is connected to the backplate to form a sealed enclosure. The spacer is situated within the enclosure and supports the two plates against forces acting towards the enclosure. The spacer can take various forms and can be constituted with various materials. In one embodiment, the spacer includes a spacer wall formed with multiple sheets of laminated material consisting of ceramic, glass-ceramic, ceramic reinforced glass, devitrifying glass, or metal coated with electrical insulation. In another embodiment, the spacer includes a spacer wall having a surface that follows a non-straight path adjacent the faceplate. In yet another embodiment, the spacer is a spacer structure through which a plurality of holes extends. The light-emitting mechanism is typically implemented with an electron-emitting cathode and light-emissive material situated over the faceplate.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: December 31, 1996
    Assignee: Silicon Video Corporation
    Inventors: Theodore S. Fahlen, Robert M. Duboc, Jr., Paul A. Lovoi
  • Patent number: 5576596
    Abstract: An optical device contains first and second plates (302 and 303), a pattern of ridges (314) situated over the first plate, light-emissive regions (313) situated in spaces between the ridges, electron-emissive elements (309) situated over the second plate, and supporting structure (308) that maintains a desired spacing between the plates. The electron-emissive elements emit electrons that strike the light-emissive regions, causing them to produce light of various colors. The ridges, which extend further away from the first plate than the light-emissive regions, are substantially non-emissive of light when hit by electrons. Each ridge includes a dark region formed with metal, ceramic, semiconductor, or/and carbide. The ridges thereby form a raised black matrix that improves contrast and color purity.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: November 19, 1996
    Assignee: Silicon Video Corporation
    Inventors: Christopher J. Curtin, Ronald S. Nowicki, Theodore S. Fahlen, Robert M. Duboc, Jr., Paul A. Lovoi
  • Patent number: 5564959
    Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: October 15, 1996
    Assignee: Silicon Video Corporation
    Inventors: Christopher J. Spindt, John M. Macaulay, Robert M. Duboc, Jr., Peter C. Searson
  • Patent number: 5541473
    Abstract: A grid which controls electron flow, placed between a field emitter cathode and fluorescent anode in a flat cathode ray tube improves focusing, and reduces the switching voltage necessary to stop electron flow. The focusing capabilities of the grid enable increased distance between the cathode and anode, permitting higher anode voltage and use of more efficient phosphors. With the grid, electron flow on/off addressing can be done with drivers operating at less than 30 V, thereby reducing capacitive power loss over prior art addressable arrays and permitting use of inexpensive CMOS control circuitry. The grid's switching capabilities enable the use of a simplified field emitter cathode structure with resistive gate films which increase emitter reliability, emitter life, and, for cathode ray tube displays, the uniformity of the display.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: July 30, 1996
    Assignee: Silicon Video Corporation
    Inventors: Robert M. Duboc, Jr., Paul A. Lovoi
  • Patent number: 5477105
    Abstract: A light-emitting structure (306) contains a main section (302), a pattern of ridges (314) situated along the main section, and a plurality of light-emissive regions (313) situated in spaces between the ridges. The light-emissive regions produce light of various colors upon being hit by electrons. The ridges, which extend further away from the main section than the light-emissive regions, are substantially non-emissive of light when hit by electrons. Each ridge includes a dark region. The ridges thereby form a raised black matrix that improves contrast and color purity. The dark region of each ridge may be formed with metal, ceramic, semiconductor, or carbide. Each ridge may include an additional region (314b) of different chemical composition than the dark region.
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: December 19, 1995
    Assignee: Silicon Video Corporation
    Inventors: Christopher J. Curtin, Ronald S. Nowicki, Theodore S. Fahlen, Robert M. Duboc, Jr., Paul A. Lovoi
  • Patent number: 5462467
    Abstract: A field-emission structure suitable for large-area flat-panel televisions centers around an insulating porous layer (24A) that overlies a lower conductive region (22) situated over insulating material of a supporting substrate (20). Electron-emissive filaments (30) occupy pores (28) extending through the porous layer. A conductive gate layer (34A) through which openings (36) extend at locations centered on the filaments typically overlies the porous layer. Cavities (38) are usually provided in the porous layer along its upper surface at locations likewise centered on the filaments.In fabricating the structure, the pores are preferably formed by etching charged-particle tracks. Electrochemical deposition is employed to selectively create the filaments in the pores. Self-alignment of the gate openings to the filaments is achieved with charged-particle track etching and/or further electrochemical processing.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: October 31, 1995
    Assignee: Silicon Video Corporation
    Inventors: John M. Macaulay, Peter C. Searson, Robert M. Duboc, Jr., Christopher J. Spindt