Patents by Inventor Robert M. Houle
Robert M. Houle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9916896Abstract: The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.Type: GrantFiled: November 1, 2016Date of Patent: March 13, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Igor Arsovski, Robert M. Houle, Michael T. Fragano, Akhilesh Patil, Van D. Butler
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Publication number: 20170200500Abstract: Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.Type: ApplicationFiled: January 7, 2016Publication date: July 13, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Igor Arsovski, Michael T. Fragano, Robert M. Houle, Thomas M. Maffitt
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Patent number: 9704575Abstract: Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.Type: GrantFiled: January 7, 2016Date of Patent: July 11, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Igor Arsovski, Michael T. Fragano, Robert M. Houle, Thomas M. Maffitt
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Patent number: 9583192Abstract: The present disclosure relates to content addressable memories (CAM), and more particularly, to a searchable CAM structure having self-reference matchline precharge and local feedback control and method of use. The present disclosure includes a structure which includes: a sense line connected to a sensing device; a feedback line connected to the sense line at a tap point between a first end and a second end of the sense line; and a local precharge controller connected to the tap point by the feedback line to control precharging of the sense line according to a state of the feedback line.Type: GrantFiled: May 25, 2016Date of Patent: February 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Igor Arsovski, Michael T. Fragano, Thomas M. Maffitt, Robert M. Houle
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Patent number: 9172371Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.Type: GrantFiled: July 23, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Igor Arsovski, Robert M. Houle
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Publication number: 20150025857Abstract: A method for predicting the power consumption of a semiconductor chip is provided. A plurality of statistical distributions characterizing a plurality of power contributing parameters for a plurality of power consuming units included in the semiconductor chip is received. A statistical distribution characterizing the power consumption is determined based on the received plurality of statistical distributions and based on the correlation between the plurality of power contributing parameters.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: International Business Machines CorporationInventors: Igor Arsovski, Robert M. Houle, Mark W. Kuemerle
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Patent number: 8611169Abstract: An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.Type: GrantFiled: December 9, 2011Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Robert M. Houle, Steven H. Lamphier, Harold Pilo
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Publication number: 20130307580Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.Type: ApplicationFiled: July 23, 2013Publication date: November 21, 2013Applicant: International Business Machines CorporationInventors: Igor ARSOVSKI, Robert M. HOULE
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Patent number: 8582351Abstract: Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.Type: GrantFiled: September 28, 2010Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: Igor Arsovski, George M. Braceras, Kevin W. Gorman, Robert M. Houle, Harold Pilo
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Publication number: 20130234754Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.Type: ApplicationFiled: March 8, 2012Publication date: September 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Igor Arsovski, Robert M. Houle
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Patent number: 8525546Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.Type: GrantFiled: March 8, 2012Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Igor Arsovski, Robert M. Houle
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Publication number: 20130148455Abstract: An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.Type: ApplicationFiled: December 9, 2011Publication date: June 13, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Houle, Steven H. Lamphier, Harold Pilo
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Patent number: 8233337Abstract: An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network.Type: GrantFiled: October 19, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Igor Arsovski, George Maria Braceras, Robert M. Houle, Harold Pilo
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Patent number: 8228713Abstract: An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.Type: GrantFiled: September 28, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Igor Arsovski, John A. Fifield, Robert M. Houle, Harold Pilo
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Publication number: 20120075918Abstract: An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Igor Arsovski, John A. Fifield, Robert M. Houle, Harold Pilo
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Publication number: 20120075919Abstract: Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Igor Arsovski, George M. Braceras, Kevin W. Gorman, Robert M. Houle, Harold Pilo
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Patent number: 7986571Abstract: An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun.Type: GrantFiled: August 18, 2010Date of Patent: July 26, 2011Assignee: International Business Machines CorporationInventors: Igor Arsovski, Michael T. Fragano, Robert M. Houle
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Patent number: 7940581Abstract: A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.Type: GrantFiled: August 23, 2010Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Igor Arsovski, Michael T. Fragano, Robert M. Houle
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Publication number: 20110090750Abstract: An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network.Type: ApplicationFiled: October 19, 2009Publication date: April 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Igor Arsovski, George Maria Braceras, Robert M. Houle, Harold Pilo
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Publication number: 20090144507Abstract: An apparatus for implementing a refreshless, embedded dynamic random access memory (eDRAM) cache device includes a cache structure having a cache tag array associated with a DRAM data cache with a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, the defined assessment period being smaller than retention time of data in the DRAM data cache. For any of the cache lines that have not been accessed during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barth, JR., Erik L. Hedberg, Robert M. Houle, Hillery C. Hunter, Peter A. Sandon