Patents by Inventor Robert M. Japp

Robert M. Japp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8499440
    Abstract: A method of making a circuitized substrate including a composite layer having a first dielectric sub-layer including a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: August 6, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papthomas
  • Patent number: 8211790
    Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: July 3, 2012
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Patent number: 8198551
    Abstract: A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: June 12, 2012
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Kostas Papathomas, John Steven Kresge, Timothy Antesberger
  • Publication number: 20120012553
    Abstract: A method for making a leadless chip carrier (LCC) for use in electronic packages having a core layer stripped of copper cladding, containing drilled clearance holes within, a layer of resin coated copper (RCC) placed on the upper surface of the core layer and a second layer of RCC placed on the lower surface of the core layer. The layers are laminated together with the RCC filling the clearance holes during lamination. A pattern is etched on the RCC and vias are drilled through the filled clearance holes and pre-plated with seed copper layers. The seed copper layers in the vias are then covered by a layer of copper plating to meet the requirements of the core buildup layer, and resin inhibiting conductive anodic filament (CAF) growth within the structure.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Kostas I. Papathomas, Cheryl Palomaki
  • Patent number: 8084863
    Abstract: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: December 27, 2011
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Publication number: 20110284273
    Abstract: A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.
    Type: Application
    Filed: May 18, 2010
    Publication date: November 24, 2011
    Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Robert M. Japp, Kostas Papathomas, John S. Kresge, Timothy Antesberger
  • Publication number: 20110207866
    Abstract: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like. The composition includes at least three resins: a halogen-free flame retardant, methyl ethyl ketone (prior to final layer formation), manganese octoate, and a coupling agent. The composition does not include a halogen or a fluoropolymer as part thereof. Dielectric layers formed from the composition are capable of withstanding the relatively high temperatures associated with lead-free solder applications. The composition may or may not include inorganic filler as part thereof.
    Type: Application
    Filed: February 25, 2010
    Publication date: August 25, 2011
    Inventors: Robert M. Japp, Kostas I. Papathomas
  • Patent number: 7931830
    Abstract: A dielectric composition which is adapted for combining with a supporting material ( e.g., fiber-glass cloth) to form a dielectric layer usable in circuitized such as PCBs, chip carriers and the like. As such a layer, it includes a resin, a predetermined percentage by weight of a filler, and, significantly, only a minor amount of bromine. A circuitized substrate comprised of one or more of these dielectric layers and one or more conductive layers is also provided.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: April 26, 2011
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas
  • Patent number: 7687722
    Abstract: A circuitized substrate including a composite layer comprising a first dielectric sub-layer comprised of a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein. A method of making such a substrate is also provided, as is a multilayered assembly including one or more such circuitized substrates, possibly in combination with other substrates. An information handling system designed for having one or more such circuitized substrates is also provided.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: March 30, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papthomas
  • Patent number: 7646098
    Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: January 12, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Publication number: 20090258161
    Abstract: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.
    Type: Application
    Filed: March 2, 2009
    Publication date: October 15, 2009
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Patent number: 7596863
    Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: October 6, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Ashwinkumar C. Bhatt, Robert J. Harendza, Robert M. Japp
  • Publication number: 20090175000
    Abstract: A circuitized substrate including a composite layer comprising a first dielectric sub-layer comprised of a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein. A method of making such a substrate is also provided, as is a multilayered assembly including one or more such circuitized substrates, possibly in combination with other substrates. An information handling system designed for having one or more such circuitized substrates is also provided.
    Type: Application
    Filed: March 2, 2009
    Publication date: July 9, 2009
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papthomas
  • Publication number: 20090173426
    Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
    Type: Application
    Filed: March 2, 2009
    Publication date: July 9, 2009
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Patent number: 7470990
    Abstract: A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: December 30, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Irving Memis, Kostas I. Papathomas
  • Patent number: 7429789
    Abstract: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also provided.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: September 30, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas
  • Patent number: 7416972
    Abstract: A method of making a circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: August 26, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Irving Memis, Kostas I. Papathomas
  • Publication number: 20080191354
    Abstract: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.
    Type: Application
    Filed: April 10, 2008
    Publication date: August 14, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Publication number: 20080191353
    Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
    Type: Application
    Filed: April 10, 2008
    Publication date: August 14, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Robert M. Japp, Voya R. Markovich, Kostas I. Papathomas, Mark D. Poliks
  • Publication number: 20080168651
    Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.
    Type: Application
    Filed: January 12, 2007
    Publication date: July 17, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Ashwinkumar C. Bhatt, Robert J. Harendza, Robert M. Japp