Abstract: A programmable controller having three well-known components used in display controls but put under the control of a programmable ‘sub-field ’ timing generator is disclosed. The three well-known components include a Phase Lock Loop (PLL) unit, a Pixel Pipe Line (PPL) unit and an embedded frame buffer. Even though these are well known and understood components, each one is implemented to support the field and sub-field concepts of field sequential color (FSC) as well as non-FSC TFT display devices. The programmable controller also includes some new components that are unique to FSC displays. These new components include a color light sequencer to control the LED controls (or whatever color light source used) and programmable Source and Gate driver controls to accommodate the extremely wide diversification between different display panels.

Abstract: A hybrid PCI_Express fabric system allows LPC bus commands and data to be sent across the PCI_Express fabric from a portable computer to its docking station. This permits the portable computer to be coupled to peripheral devices connected to the docking station without additional connectors on the portable computer and the docking station.

Abstract: A method of providing a low cost quantized nonlinear scaler for a continuous curve includes the steps of providing a quantized coefficient table representing an approximation of the nonlinear continuous curve; applying the table in hardware to locate coefficients in the table, and applying the coefficients to a scaling pipeline to get scaled data. The nonlinear approximation in the table is achieved by following the rules that the sampled data must be consistent, the quantization points must be consistent, the coefficient curve must be symmetric about its centerline, and the quantization values must be selected so that the sum of all coefficients values in the coefficient curve over all the source points for a given resultant point is always equal to a normalization value.

Abstract: A Virtual Frame Buffer control system and method for cascading several display controllers on one LCD panel. The Virtual Frame Buffer is composed of all the memory in all the controller/memory/source driver chips (in a tiled pattern) for the associated processor to read and write in. The control system also includes hardware clipping controls in each of the controller/memory/source driver chips. The Virtual Frame Buffer and hardware clipping control placement substantially reduces programming problems associated with prior art solutions for cascading LCD controller/memory/source driver devices.

Abstract: A programmable controller having three well-known components used in display controls but put under the control of a programmable ‘sub-field ’ timing generator is disclosed. The three well-known components include a Phase Lock Loop (PLL) unit, a Pixel Pipe Line (PPL) unit and an embedded frame buffer. Even though these are well known and understood components, each one is implemented to support the field and sub-field concepts of field sequential color (FSC) as well as non-FSC TFT display devices. The programmable controller also includes some new components that are unique to FSC displays. These new components include a color light sequencer to control the LED controls (or whatever color light source used) and programmable Source and Gate driver controls to accommodate the extremely wide diversification between different display panels.

Abstract: A Virtual Frame Buffer control system and method for cascading several display controllers on one LCD panel. The Virtual Frame Buffer is composed of all the memory in all the controller/memory/source driver chips (in a tiled pattern) for the associated processor to read and write in. The control system also includes hardware clipping controls in each of the controller/memory/source driver chips. The Virtual Frame Buffer and hardware clipping control placement substantially reduces programming problems associated with prior art solutions for cascading LCD controller/memory/source driver devices.

Abstract: A system and method for reducing bottlenecks on a computer bus, by offloading specific types of high-bandwidth data from the system bus and passing that data directly to specialized target busses. In the computer system, the system bus, typically a PCI bus, is monitored for addresses corresponding to specific target devices. When these addresses are detected, the corresponding data is diverted from the system bus to the appropriate specialized bus. By doing so, bandwidth across the system bus is reduced, and the specialized data, which may be time-sensitive or real-time audio or video, is passes rapidly to the appropriate processor.

Abstract: A method of providing a low cost quantized nonlinear scaler for a continuous curve includes the steps of providing a quantized coefficient table representing an approximation of the nonlinear continuous curve; applying the table in hardware to locate coefficients in the table, and applying the coefficients to a scaling pipeline to get scaled data. The nonlinear approximation in the table is achieved by following the rules that the sampled data must be consistent, the quantization points must be consistent, the coefficient curve must be symmetric about its centerline, and the quantization values must be selected so that the sum of all coefficients values in the coefficient curve over all the source points for a given resultant point is always equal to a normalization value.

Abstract: A memory system 104 includes an array 200 of memory cells arranged in rows and columns. Circuitry 208 is included for selectively performing logic operations on a bit of data stored in a selected cell using a bit of received modifying data and mode data bit for selecting a logic operation for performance. Circuitry 208 for performing logic operations is operable during an AND logic operation to write data into the cell when the bit of modifying data is a logic zero and maintaining an existing bit stored in the cell when the bit of modifying data is a logic one. Also included is circuitry 207, 210 for receiving and latching the mode data bit and the modifying data through a single port.

Abstract: A memory system 104 includes an array 200 of memory calls arranged in rows and columns and circuitry 208 for selectively performing logic operations on a bit of data stored in a selected call using a bit of received modifying data and a mode data bit for selecting a logic operation for performance. Circuitry 208 for modifying during an OR logic operation writing bit of the modifying data into the cell when the bit of modifying data is a logic one and maintaining an existing bit stored in call when the bit of modifying data is a logic zero. Memory system 104 further includes circuitry 207, 210 for receiving and latching the mode data and the modifying data through a single port.

Abstract: Sensing circuitry including a sense amplifier 400 for latching a bit of data on a true bit line and a complementary bit of data on a complementary bit line. Circuitry 403, 404, 405 is included for performing boolean operations on bit of data latched in sense amplifier 400 in response to a bit of modifying data. Circuitry 403, 404, 405 during an AND operation pulls down the true bit line when the bit of modifying data a logic 0.

Abstract: A memory system 104 is provided which includes an array 200 of memory cells arranged in rows and columns. Circuitry 207, 208, 209, 210 is also provided for selectively performing logic operations on a bit of data stored in a selected memory cell using a bit of received modifying data. Circuitry 207, 208, 209, 210 for performing logic operations is operable during an AND operation to write the bit of modifying data into the selected memory cell when the bit of modifying data is a logic zero and maintains an existing bit stored in the selected cell when the bit of modifying data is a logic one.

Abstract: A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.

Abstract: A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: Methods are provided for transferring a stream of video data from a video data source to a display interface unit 20. A video data word is clocked into a first-in-first-out memory 30 by a first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: A method is provided for generating a composite video data stream. A first data stream composed of a sequence of frames of video data each having an x-dimension of a preselected number of pixels and a y-dimension of a preselected number of pixels is received. A second data stream composed of a sequence of frames of video data each having a x-dimension of a preselected number of pixels and a y-dimension of a preselected number of pixels is also received. The x- and y-dimensions of the frames of the first data stream are downscaled to produce a sequence of first blocks of pixels. The x- and y-dimensions of the frames of the second data stream are downscaled to produce a sequence of second blocks of pixels. The first blocks are written into a first object buffer associated with a first memory space during first and third ones of four processing phases using a set of counters associated with the first object buffer.

Abstract: A method is provided for displaying data received as a composite video data stream, each frame of the composite data stream being composed of a field of data defining a first video display and a subsequent field defining a second video display. The composite video data stream is received and during first and third phases of a set of processing phases, the fields of data defining the first video display are stored in a first object buffer in memory. During second and fourth phases of the set of processing phases, the fields of data defining the second display are stored in a second object buffer in memory. During the first and third phases, the fields of data stored in the first object buffer are retrieved to generate the first display and during the second and fourth phases, the fields of data stoned in the second object buffer are retrieved to generate the second display.

Abstract: A method is provided for generating a plurality of displays from a composite video data stream comprising a plurality of frames each including two portions, a first portion of each frame containing data defining even fields of respective first and second displays and a second one of the portions of each frame containing data defining odd fields of the first and second displays. During first and second phases of a set of processing phases, data defining the odd and even fields of the first display are extracted from each received frame. Also during the first and third phases, the extracted data defining the odd and even fields of the first display are written into a first object buffer. During second and fourth phases of the set of processing phases, data defining the odd and even fields of the second display are extracted from each received frame. Also during the second and fourth phases, the extracted data defining the odd and even fields of the second display is written into a second object buffer.

Abstract: A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.