Abstract: A method is provided for displaying data received as a composite video data stream, each frame of the composite data stream being composed of a field of data defining a first video display and a subsequent field defining a second video display. The composite video data stream is received and during first and third phases of a set of processing phases, the fields of data defining the first video display are stored in a first object buffer in memory. During second and fourth phases of the set of processing phases, the fields of data defining the second display are stored in a second object buffer in memory. During the first and third phases, the fields of data stored in the first object buffer are retrieved to generate the first display and during the second and fourth phases, the fields of data stoned in the second object buffer are retrieved to generate the second display.

Abstract: A method is provided for generating a plurality of displays from a composite video data stream comprising a plurality of frames each including two portions, a first portion of each frame containing data defining even fields of respective first and second displays and a second one of the portions of each frame containing data defining odd fields of the first and second displays. During first and second phases of a set of processing phases, data defining the odd and even fields of the first display are extracted from each received frame. Also during the first and third phases, the extracted data defining the odd and even fields of the first display are written into a first object buffer. During second and fourth phases of the set of processing phases, data defining the odd and even fields of the second display are extracted from each received frame. Also during the second and fourth phases, the extracted data defining the odd and even fields of the second display is written into a second object buffer.

Abstract: A processing system 100 is provided which includes a memory 107 and memory control circuitry 203. Packing circuitry 215 is operable to receive a stream of video data words in a first YUV format and convert those video data words into a plurality of packed words in a second YUV format. Memory control circuitry 203 is operable to simultaneously store the plurality of packed YUV words in memory 107 in the second format along with a plurality of RGB words.

Abstract: A method is provided for generating a output composite video data stream. During a first phase of a set of processing phases, a frame of first video data is received and then downscaled to produce a first block of data. Also during the first phase, the first block is stored and then retrieved from a first memory space. The first block is next upscaled and then output as a first field of a composite video data stream. During a second phase of the set of processing phases, a frame of second video data is received and downscaled to produce a second block of data. Also during the second phase, the second block of data is stored and then retrieved from a second memory space. The second block is next upscaled during the second processing phase and then output as a second field of the composite video stream.

Abstract: A digital video editor employing a single chip special-purpose digital video processing unit (VPU) having the capability to combine several different digital video input signals into a single digital video output signal is disclosed. The VPU comprises a microprocessor operating under a set of instructions which is operative for receiving, storing and manipulating portions of an incoming digital video signal and a delay circuit, coupled to the microprocessor, for delaying execution of a particular instruction if a particular portion upon which the instruction is to operate has not yet been stored. The VPU processes multiple digitized video signals in real time in a time-sharing fashion because its processing speed is substantially greater than the rate at which it receives video data and processes multiple picture elements of a single digital stream simultaneously. In a preferred environment, The VPU operates in conjunction with an IBM compatible personal computer, an inexpensive general purpose computer.

Abstract: A pixel color processor that performs supplemental graphical processing duties in a video unit in a computer system. The pixel color processor is interfaced between a processor and video memory and performs pixel string manipulation and color management duties on the pixel color data at the direction of the processor, thereby freeing up the processor of these duties. The memory address space of the processor includes a monochrome memory area which maps onto the full-depth packed-pixel video memory. When the processor performs operations on this monochrome area, the pixel color processor intercepts the addresses data generated by the processor and performs the pixel block transfers.