Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die.

Abstract: A CMOS memory is disclosed which employs a column selector circuit that prevents write disturb in shared column EPROMs. When a selected memory transistor is programmed, disturb is prevented by selecting all columns on the source side of the selected memory transistor to be tied to the source programming voltage, and selecting all columns on the drain side of the selected memory transistor to be tied to the drain programming voltage. By reducing voltage differentials across non-selected memory transistors, write disturb is prevented. This may be implemented by employing shorting devices between all adjacent columns. When a memory transistor is selected, all the shorting devices except the one between the source and drain columns of the selected memory cell are enabled. This may be further improved to minimize the number of required select lines by employing a shorting device comprising transistors controlled by the normal select lines.