Patents by Inventor Robert M. Walker

Robert M. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11369060
    Abstract: An agricultural vehicle including at least one threshing rotor and an auger bed located underneath the at least one threshing rotor. The auger bed has a working position and a cleaning position. The auger bed includes a frame, a plurality of augers rotatably coupled to and supported by the frame, and a trough portion moveably connected to the frame. In the working position the bottom surface of the trough portion is positioned underneath the plurality of augers and in the cleaning position the entire trough portion is moved relative to the frame so that the bottom surface of the trough portion is not positioned underneath at least a portion of the plurality of augers, creating an open space underneath the portion of the plurality of augers for allowing an unwanted material to pass therethrough.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: June 28, 2022
    Assignee: CNH Industrial America LLC
    Inventors: Curtis F. Hillen, Herbert M. Farley, Andrews V. Lauwers, Robert S. Boyd, III, Eric L Walker
  • Patent number: 11366762
    Abstract: The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker
  • Patent number: 11340787
    Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, James A. Hall, Jr.
  • Publication number: 20220156209
    Abstract: The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Frank F. Ross, Robert M. Walker
  • Publication number: 20220147262
    Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Publication number: 20220137882
    Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Inventors: Robert M. Walker, Frank F. Ross
  • Patent number: 11314643
    Abstract: A request to perform a write operation to write data at a memory sub-system is received. Responsive to the request to perform the write operation, the data is stored at a cache portion of cache memory of the memory sub-system. A duplicate copy of the data is stored at a write buffer portion of cache memory. An entry of the write buffer record is recorded that maps a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory. A memory operation is performed at the memory sub-system based at least in part on the write buffer record.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker
  • Publication number: 20220113887
    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.
    Type: Application
    Filed: October 26, 2021
    Publication date: April 14, 2022
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Patent number: 11301380
    Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 12, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Robert M. Walker, Ashay Narsale
  • Patent number: 11301383
    Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 12, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Patrick A. La Fratta, Cagdas Dirik, Laurent Isenegger, Robert M. Walker
  • Patent number: 11288214
    Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert M. Walker
  • Publication number: 20220083236
    Abstract: The present disclosure includes apparatuses and methods related to a memory system with cache line data. An example apparatus can store data in a number of cache lines in the cache, wherein each of the number of lines includes a number of chunks of data that are individually accessible.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Cagdas Dirik, Robert M. Walker
  • Publication number: 20220075558
    Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 10, 2022
    Inventors: Elliott C. Cooper-Balis, Robert M. Walker, Paul Rosenfeld
  • Patent number: 11256437
    Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Publication number: 20220050616
    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Patent number: 11243889
    Abstract: The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker
  • Patent number: 11237995
    Abstract: The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Frank F. Ross, Robert M. Walker
  • Publication number: 20220027270
    Abstract: A request to perform a write operation to write data at a memory sub-system is received. Responsive to the request to perform the write operation, the data is stored at a cache portion of cache memory of the memory sub-system. A duplicate copy of the data is stored at a write buffer portion of cache memory. An entry of the write buffer record is recorded that maps a location of the duplicate copy of the data stored at the write buffer portion to a location of the data stored at the cache portion of the cache memory. A memory operation is performed at the memory sub-system based at least in part on the write buffer record.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventor: Robert M. Walker
  • Publication number: 20220019533
    Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Cagdas Dirik, II, Laurent Isenegger, Robert M. Walker
  • Publication number: 20220019360
    Abstract: A method is described that includes receiving a plurality of streams of memory requests and each stream is associated with a source. The method further includes determining a bandwidth allocation for each stream, wherein each allocation represents a portion of a total bandwidth of a memory component managed by the subsystem and each allocation indicates a priority of a corresponding stream based on a corresponding source of each stream and assigning a set of credits to each stream based on the bandwidth allocations. The method also includes determining a memory command from a queue for issuance, wherein each memory command in the queue is associated with a stream and determining the memory command is based on the credits assigned to each stream such that commands associated with a stream with a higher number of credits is given priority for issuance over commands associated with a stream with a lower number.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert M. Walker