Abstract: A processing device, operatively coupled with a memory device, retrieves data from the memory device for merging at one or more sectors of a cache line in a cache, wherein the cache line comprises a plurality of sectors. The processing device determines, based on one or more bits associated with each sector of the cache line, whether each sector of the cache line is configured with at least one of a write protection mode and enable mode, respectively. The processing device writes the data from the memory device to each sector of the cache line using the at least one of the write protection mode or the enable mode.

Abstract: A system comprising an interface between a host and a device, wherein the interface is configured to reorder messages to package flits to reduce or eliminate underutilized bandwidth in one or both directions of a bidirectional link. In one example, the interface is in accordance with the CXL specification, and the host and the device (e.g., a memory device) include CXL-compliant controllers to pack and unpack flits.

Abstract: Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

Abstract: Provided is a memory system and a method for improving bandwidth utilization in the memory system that includes receiving, at a host processor, a first read request from an input buffer, determining a combinable address range associated with the first read request, identifying one or more additional read requests in the input buffer having access addresses within the combinable address range, when one or more additional read requests are identified, modifying the first read request to represent the one or more additional read requests using a bit vector indicating their presence within the combinable address range, packing the modified first read request into a single slot of an outgoing flit, and transmitting the flit over an outgoing communication link.

Abstract: Apparatuses and methods related to port arbitration of a memory system are described. A memory system can receive a first number of transactions and a second transaction from a first traffic stream and a third number of transactions and a fourth transaction from a second traffic stream. The memory system can process the first number of transactions at least partially concurrently with the third number of transactions. Responsive to a total quantity of transactions of the first number of transactions and the second transaction being at least a threshold quantity of transactions, the second transaction can be processed by the memory system and, subsequent to processing the second transaction, the fourth transaction can be processed by the memory system.

Abstract: An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can include row hammer detection circuitry configured to receive signaling indicative of a row activation command having a row address, increment a row counter corresponding to the row address stored in a stored in a data structure in a register or storage device, determine whether the incremented row counter is greater than a row hammer threshold, and issue a row hammer mitigation command to mitigate row hammer.

Abstract: Apparatuses and methods related to port arbitration of a memory system are described. A memory system can receive a first number of transactions and a second transaction from a first traffic stream and a third number of transactions and a fourth transaction from a second traffic stream. The memory system can process the first number of transactions at least partially concurrently with the third number of transactions. Responsive to a total quantity of transactions of the first number of transactions and the second transaction being at least a threshold quantity of transactions, the second transaction can be processed by the memory system and, subsequent to processing the second transaction, the fourth transaction can be processed by the memory system.

Abstract: Provided is a system comprising a communication interface between a host and a device, wherein the header of a first memory request transmitted on the forward link of the communication interface encodes, in a bit vector, addresses to be read for a plurality of second memory requests. Combining one or more read requests with another request such that a single request header is transmitted for a plurality of respective requests provides for more efficient use of the forward link bandwidth. Corresponding methods are also described.

Abstract: An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can include row hammer detection circuitry configured to receive signaling indicative of a row activation command having a row address, increment a row counter corresponding to the row address stored in a stored in a data structure in a register or storage device, determine whether the incremented row counter is greater than a row hammer threshold, and issue a row hammer mitigation command to mitigate row hammer.

Abstract: An access tracker configured to receive a request to access a page, determine whether a page identification (ID) associated with the page is in the access tracker, increment an access count of the page in response to determining the page ID is in the access tracker, sort a number of page IDs based on an access count of each page ID, and determine whether a different page is hot or cold in response to sorting the number of page IDs.

Abstract: Memory controller commands to be sent to a memory device may be prioritized based one or more factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read) are prioritized over other types of commands (e.g., write). The policy may be modified so when deciding which bank to open, the bank with the oldest read command is opened. While continuing to issue commands per this modified FRFCFS policy, the controller may keep track of banks whose pages are ready to receive their respective read commands. Once a number of ready banks meets or exceeds a threshold, issuance of write commands are paused and read commands for the ready banks are issued.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

Abstract: Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.

Abstract: There are provided a system and a method for maintaining the integrity of a memory component that includes receiving, by a memory controller, a plurality of memory requests including at least one write request, allocating a data block into a buffer cache to cache the at least one write request, detecting whether sufficient time has elapsed beyond a predetermined threshold, in response to sufficient time having elapsed beyond the predetermined threshold, flagging a backend memory as being available; and in response to the flagging, fetching the at least one write request to write data to the memory component.

Abstract: There are provided a system and a method for write or store driven buffer cache memory for a Reliable Array of Independent Disks (RAID)-protected memory. For example, there is provided a system that can include a RAID subsystem configured to maintain the integrity of a section of a memory. The system can further include a buffer memory communicatively coupled to the RAID subsystem. And the RAID subsystem may be configured to limit a frequency of RAID access memory command amplification by accessing the buffer memory the subsystem is performing an operation configured to maintain the integrity of the section of the memory.