Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.

Abstract: A method includes enqueuing host commands of a first type and a second type in a command queue of a host memory controller and preventing a subsequent host command of the first type from being inserted into the command queue responsive to determining that a quantity of host commands of the first type and enqueued in the command queue having met a criterion.

Abstract: A method comprising directing, via a memory manager, an address associated with data to be written to a cold memory map, receiving the data at a memory device, and writing the data to the memory device in response to the memory manager identifying the data as cold data in response to writing the address associated with the data to the cold memory map.

Abstract: An access tracker configured to receive a request to access a page, determine whether a page identification (ID) associated with the page is in the access tracker, increment an access count of the page in response to determining the page ID is in the access tracker, sort a number of page IDs based on an access count of each page ID, and determine whether a different page is hot or cold in response to sorting the number of page IDs.

Abstract: A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.

Abstract: A method includes allocating, via a tier allocation component, a first portion of data to a first tier memory component and writing the first portion of data to the first tier memory component in response to a first tier free list having an available entry. The method further includes evicting a second portion of data from the first tier memory component in response to the first tier free list being empty when the first portion of data is allocated to the first tier memory component and writing the first portion of data to the first tier memory component in response to evicting the second portion of data.

Abstract: A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device.

Abstract: A method includes accessing a first memory component of a memory sub-system via a first interface, accessing a second memory component of the memory sub-system via a second interface, and transferring data between the first memory component and the second memory component via the first interface. The method further includes initially writing data in the first memory component via a first address window and accessing data in the second memory component via a second address window in response to caching the data in first memory component to the second memory component, wherein caching the data in the first memory component to the second component includes changing an address for the data from the first address window to the second address window.

Abstract: A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

Abstract: A method is described that includes receiving a plurality of streams of memory requests and each stream is associated with a source. The method further includes determining a bandwidth allocation for each stream, wherein each allocation represents a portion of a total bandwidth of a memory component managed by the subsystem and each allocation indicates a priority of a corresponding stream based on a corresponding source of each stream and assigning a set of credits to each stream based on the bandwidth allocations. The method also includes determining a memory command from a queue for issuance, wherein each memory command in the queue is associated with a stream and determining the memory command is based on the credits assigned to each stream such that commands associated with a stream with a higher number of credits is given priority for issuance over commands associated with a stream with a lower number.

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol with programmable buffer and cache size. An example apparatus can program a resister to define a size of a buffer in memory, store data in the buffer in a first portion of the memory defined by the register, and store data in a cache in a second portion of the memory.

Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: Methods, systems, and apparatus for command scheduling in a memory subsystem according to a selected scheduling ordering are described. Scheduling orderings are determined for a set of commands, where a scheduling ordering identifies an order by which a memory subsystem controller is to issue each command in the set of commands to the memory device. Scores are calculated for the scheduling orderings. A score of the plurality of scores includes a measure of performance of execution of the set of commands according to the scheduling ordering. A scheduling ordering is selected from the scheduling orderings based on the scores, and a command is issued to the memory device according to the scheduling ordering.

Abstract: Methods, systems, and apparatus for command scheduling in a memory subsystem according to a selected scheduling ordering are described. Scheduling orderings are determined for a set of commands, where a scheduling ordering identifies an order by which a memory subsystem controller is to issue each command in the set of commands to the memory device. Scores are calculated for the scheduling orderings. A score of the plurality of scores includes a measure of performance of execution of the set of commands according to the scheduling ordering. A scheduling ordering is selected from the scheduling orderings based on the scores, and a command is issued to the memory device according to the scheduling ordering.

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).