Patents by Inventor Robert Nickerson
Robert Nickerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12557683Abstract: A die package comprises a substrate comprising a solder pad element, a semiconductor die coupled to the substrate, a solder layer comprising a first solder material deposited on the solder pad element, the first solder material having a first melting temperature, and an interconnect ball comprising a second solder material deposited on the solder layer, the second solder material having a second melting temperature that is less than the first melting temperature.Type: GrantFiled: December 20, 2021Date of Patent: February 17, 2026Assignee: Intel CorporationInventors: Mukund Ayalasomayajula, Dinesh Padmanabhan Ramalekshmi Thanu, Rui Zhang, Xiao Lu, Robert Nickerson, Patrick Neel Stover
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Publication number: 20250391754Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.Type: ApplicationFiled: August 28, 2025Publication date: December 25, 2025Inventors: Debendra MALLIK, Robert L. SANKMAN, Robert NICKERSON, Mitul MODI, Sanka GANESAN, Rajasekaran SWAMINATHAN, Omkar KARHADE, Shawna M. LIFF, Amruthavalli ALUR, Sri Chaitra J. CHAVALI
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Patent number: 12476174Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.Type: GrantFiled: September 29, 2023Date of Patent: November 18, 2025Assignee: Intel CorporationInventors: Debendra Mallik, Robert L Sankman, Robert Nickerson, Mitul Modi, Sanka Ganesan, Rajasekaran Swaminathan, Omkar Karhade, Shawna M. Liff, Amruthavalli Alur, Sri Chaitra J. Chavali
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Patent number: 12406914Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.Type: GrantFiled: December 30, 2022Date of Patent: September 2, 2025Assignee: Intel CorporationInventors: Debendra Mallik, Robert L. Sankman, Robert Nickerson, Mitul Modi, Sanka Ganesan, Rajasekaran Swaminathan, Omkar Karhade, Shawna M. Liff, Amruthavalli Alur, Sri Chaitra J. Chavali
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Publication number: 20240030116Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.Type: ApplicationFiled: September 29, 2023Publication date: January 25, 2024Inventors: Debendra MALLIK, Robert L. SANKMAN, Robert NICKERSON, Mitul MODI, Sanka GANESAN, Rajasekaran SWAMINATHAN, Omkar KARHADE, Shawna M. LIFF, Amruthavalli ALUR, Sri Chaitra J. CHAVALI
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Publication number: 20230197659Abstract: A die package comprises a substrate comprising a solder pad element, a semiconductor die coupled to the substrate, a solder layer comprising a first solder material deposited on the solder pad element, the first solder material having a first melting temperature, and an interconnect ball comprising a second solder material deposited on the solder layer, the second solder material having a second melting temperature that is less than the first melting temperature.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Inventors: Mukund Ayalasomayajula, Dinesh Padmanabhan Ramalekshmi Thanu, Rui Zhang, Xiao Lu, Robert Nickerson, Patrick Neel Stover
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Publication number: 20230138543Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.Type: ApplicationFiled: December 30, 2022Publication date: May 4, 2023Inventors: Debendra MALLIK, Robert L. SANKMAN, Robert NICKERSON, Mitul MODI, Sanka GANESAN, Rajasekaran SWAMINATHAN, Omkar KARHADE, Shawna M. LIFF, Amruthavalli ALUR, Sri Chaitra J. CHAVALI
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Publication number: 20220344247Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.Type: ApplicationFiled: July 11, 2022Publication date: October 27, 2022Inventors: Debendra MALLIK, Robert L. SANKMAN, Robert NICKERSON, Mitul MODI, Sanka GANESAN, Rajasekaran SWAMINATHAN, Omkar KARHADE, Shawna M. LIFF, Amruthavalli ALUR, Sri Chaitra J. CHAVALI
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Patent number: 11462527Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.Type: GrantFiled: July 30, 2018Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Kumar Abhishek Singh, Zhaozhi Li, Thomas J. Debonis, Robert Nickerson, Rees Winters
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Patent number: 11430724Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.Type: GrantFiled: December 30, 2017Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: Debendra Mallik, Robert L. Sankman, Robert Nickerson, Mitul Modi, Sanka Ganesan, Rajasekaran Swaminathan, Omkar Karhade, Shawna M. Liff, Amruthavalli Alur, Sri Chaitra J. Chavali
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Publication number: 20200273784Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.Type: ApplicationFiled: December 30, 2017Publication date: August 27, 2020Inventors: Debendra MALLIK, Robert L. SANKMAN, Robert NICKERSON, Mitul MODI, Sanka GANESAN, Rajasekaran SWAMINATHAN, Omkar KARHADE, Shawna M. LIFF, Amruthavalli ALUR, Sri Chaitra J. CHAVALI
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Publication number: 20200251462Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: ApplicationFiled: November 11, 2019Publication date: August 6, 2020Inventors: Russell Mortensen, Robert Nickerson, Nicholas R. Watts
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Publication number: 20200035658Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.Type: ApplicationFiled: July 30, 2018Publication date: January 30, 2020Inventors: Kumar Abhishek SINGH, Zhaozhi LI, Thomas J. DEBONIS, Robert NICKERSON, Rees WINTERS
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Publication number: 20190104610Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first substrate comprising a first die, wherein an underfill material is disposed on a first surface of the first substrate adjacent the first die; and a second substrate disposed on the first substrate, wherein the second substrate comprises at least one opening disposed over the first die, wherein the at least one opening is at least partially filled with the underfill material.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: Robert Nickerson, Nitin Deshpande, Omkar Karhade, Thomas De Bonis
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Patent number: 10231338Abstract: Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.Type: GrantFiled: June 24, 2015Date of Patent: March 12, 2019Assignee: INTEL CORPORATIONInventors: Naga Sivakumar Yagnamurthy, Huiyang Fei, Pramod Malatkar, Prasanna Raghavan, Robert Nickerson
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Patent number: 9666549Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.Type: GrantFiled: October 9, 2015Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Chia-Pin Chiu, Xiaorong Xiong, Linda Zhang, Robert Nickerson, Charles Gealer
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Publication number: 20160381800Abstract: Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.Type: ApplicationFiled: June 24, 2015Publication date: December 29, 2016Inventors: Naga Sivakumar Yagnamurthy, Huiyang Fei, Pramod Malatkar, Prasanna Raghavan, Robert Nickerson
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Patent number: 9446975Abstract: Systems and methods for treating carbon-containing waste materials include a gasifying system, a drier system for pre-drying the material, and an energy-recovery system for recovering waste heat and/or producer gas from the gasifying system/method for use in pre-drying the material. The energy-recovery system can include a recirculation system for recovering the waste heat and/or a thermal oxidizer or other combustion device for burning the producer gas, along with a heat-transfer-loop for transferring the recovered heat energy to the drier for pre-drying the material. In another aspect of the invention, the gasifying systems and methods use a thermal-screw conveyor with a product chamber and rotary thermal screws, and an oxygen-delivery system configured for delivering oxygen into the product chamber for immediate absorption into the material, with or without the dryer system and/or the energy-recovery system.Type: GrantFiled: October 22, 2012Date of Patent: September 20, 2016Assignee: THERMA-FLITE, INC.Inventors: Robert Nickerson, Mike Potter, John Whitney
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Patent number: 9290330Abstract: A system for treating a material includes first and second screw conveyors each having a rotary shaft and a helical flight extending radially outward therefrom, the flighting of the screw conveyors overlapping with each other, and first and second actuators operably coupled to the first and second screw conveyors in a one-to-one dedicated relationship to rotationally drive the screw conveyors independently of each other. In typical embodiments, also included is a system for varying the clocking position of the screw conveyors relative to each other, wherein the screw conveyor flights are axially adjusted with respect to each other between a normal position and an advanced and/or retarded position. Also disclosed are methods of varying the axial position of the screw conveyor flights with respect to each other between the normal and advanced and/or retarded positions.Type: GrantFiled: April 29, 2014Date of Patent: March 22, 2016Assignee: THERMA-FLITE, INC.Inventors: Robert Nickerson, John Whitney
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Publication number: 20160043049Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.Type: ApplicationFiled: October 9, 2015Publication date: February 11, 2016Inventors: Chia-Pin Chiu, Xiaorong Xiong, Linda Zhang, Robert Nickerson, Charles Gealer