Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.

Abstract: A method for programming a semiconductor element in a semiconductor structure such as an IC involves reducing the backside thickness of the substrate and directing an energy beam through the backside at an opaque component of the semiconductor element. A support structure mounted on the semiconductor structure provides support during and after the thinning operation. Alternatively, the substrate can be thinned only under the semiconductor element, leaving the rest of the substrate thick enough to maintain structural integrity. The energy beam heats the opaque component. The prior thinning operation minimizes heat dissipation away from the semiconductor element, so that dopant diffusion occurs, changing the electrical characteristics of the semiconductor element. By modifying selected elements in this manner, a semiconductor structure can be permanently programmed, even if it does not include non-volatile memory. Additionally, security is enhanced since the programming leaves no visible signs.

Abstract: A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Abstract: A wafer of integrated circuits under test (ICUT) is tested by supplying power to the ICUTs using power and ground traces that extend between rows of the ICUTs in scribe streets. Test information is supplied to each ICUT by transmitting the test information optically onto the entire wafer. A diode on each ICUT receives the optical test information. The ICUT uses the test information to perform a self-test. Each ICUT has a diode for transmitting optical test information. All ICUTs on the wafer transmit results of the self-tests at the same time. A test device receives the optical test information and identifies the information from each of the many ICUTs, one from another. An entire wafer of ICUTs is therefore tested simultaneously without using a probe card either to power an ICUT or to supply test information to or receive test information from an ICUT.

Abstract: An external fiber optic cable is snap fit onto the connector of the integrated circuit package, light passes from an optical fiber in the external cable, through the first optical fiber and to the reflecting surface where the light is reflected by the reflecting surface so that it is incident on the photodetector whereas the photodetector converts the light into an electrical signal and the electrical signal is then communicated via a micro pad structures from the optoelectronic die.

Abstract: A die assembly contains multiple stacked dice bonded together by a large number of metal posts. A first die has a plurality of metal posts oriented orthogonally to a planar surface of the first die. The metal posts protrude from the first die out beyond the surface. Similarly, a second die also has a plurality of metal posts protruding from a surface. The first die is coupled to the second die in an oxygen-free atmosphere such that each protruding metal post of the first die contacts a protruding metal post of the second die. By applying pressure, cold welds are formed between corresponding metal posts of the first and second dice. The first die and the second die are held together by the metal posts without an adhesive. In one embodiment, some of the metal posts do not conduct signals between the first and second dice.

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: A method is described for measuring localized operating temperatures and voltages on an integrated circuit. The integrated circuit includes an oscillator circuit with a frequency that varies with temperature and/or applied voltage. The frequency of the oscillator is then determined, using a constant voltage, for a number of temperatures to establish a known relationship between oscillation frequency and temperature. Once the relationship is known, a similar oscillator is included within or adjacent a second circuit of the integrated circuit. The operating temperature or operating voltage of the second circuit may then be determined by monitoring the frequency of the oscillator while the second circuit is operational.

Abstract: Described is a user-controlled, variable-delay interconnect structure for a programmable logic device (PLD), and a method for using this structure. In accordance with the invention, the signal propagation delays for selected signal paths can be precisely adjusted either while the PLD is being programmed or while the PLD is operating as a logic device. The delays are adjusted by selectively connecting otherwise unused interconnect lines to the signal path to increase the capacitive load on the interconnect lines that define the signal path. The ability to control the load on selected signal paths advantageously enables a user to precisely match the signal propagation delays of two or more signal paths. In one embodiment, the loads of selected signal paths can be modified while the FPGA is operational.

Abstract: A reference ring oscillator circuit (RROC) is used to determine timing characteristics of a test interconnect structure in an integrated circuit. The RROC includes an odd number of inverters coupled together in a ring manner and has defined test segments at which a test interconnect can be loaded. Reference timing characteristics of the unloaded RROC are determined according to a calibration method including the steps of: (a) directly measuring signal propagation delay through each segment of the RROC; (b) modeling each test segment using an RC tree type reference circuit model having reference elements; (c) simulating the reference circuit model to provide a functional relationship between two reference capacitors; (d) defining upper and lower bounds for propagation delay through the test segment in terms of the reference elements; (e) determining values for the reference capacitor elements; and (f) measuring a reference frequency of oscillation of the unloaded RROC.