Abstract: An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose FPGA device or fabric, this fast reconfigurability is normally implemented by special reconfiguration support circuitry and/or additional configuration memory. Unfortunately, this flexibility requires a large amount of programmable routing resource and silicon area—limiting the viability in volume production applications. This invention describes how multi-program FPGA functionalities may be migrated to smaller die by constructing implementations with a hybrid FPGA/ASIC interconnect structure.

Abstract: A software programmable DSP with a field programmable instruction set is described where customized instructions can be created, or certain existing instructions can be modified, at the user's location after taking delivery of the processor. The FPGA fabric used to implement the reprogrammable instructions is restricted to supporting the software-programmable DSP—never functioning as an independent coprocessor—and therefore enabling the reprogrammable instructions to exist in the normal stream of DSP software execution. DSP-type functions implemented in the FPGA fabric are also restricted to being automatically generated such that they are synchronous with the processor clocks—enabling easy conversion to an ASIC.

Abstract: Electro-mechanical and electronically controlled access devices are described for controlling access to a building, premises or area in a secure manner such that a subject who is deemed ineligible for access will be barred entry and may be optionally retained. The devices can contain multiple rotatable door panels, which can be positioned behind one another. The door panels can be controlled by mechanized arms or other control devices in order to control the passage through the device. The direction of flow through a device according to these embodiments is electronically controlled and may be changed at any point in time. At any instant in time, the flow through the device is unidirectional. Multiple devices can be stacked together to form clusters, which can be controlled according to traffic, time of day, or other factors.

Abstract: A miniature surveillance balloon system is described that can be used in military and public safety situations for real-time observations. They are as small as feasibly possible, low-cost and expendable, and typically are deployed in clusters. Balloons may act individually or alternately clusters may act robotically (in unison) without command input at times. Video surveillance information is preprocessed and then sent via wireless communications links. Batteries and/or gas cylinders may be selectively jettisoned to facilitate vertical movement. Balloons may optionally have thruster mechanisms to facilitate lateral movement which may in some embodiments be powered by a source of combustible gas which is also used for providing lift.

Abstract: A system is described that enables the user to deal with an intrusion into their home without having to personally confront the intruder. Given the night-time nature of many intruder events, a display and control unit is disclosed that is suitable for residing on a bedside table, typically in the Master Bedroom, performing a remote viewing and control function. Various locations within the particular home are represented by buttons such that the user can easily choose the location(s) to be viewed and can verify, among other things, the presence of an intruder. Motion detection is various rooms may be included and viewing can be enhanced by lights controlled from this unit. User interface features are included that are simple to operate when the user is half-awake. Surveillance and control features may be combined with common bedside appliance functions including a clock-radio, a television, or a telephone.

Abstract: A binning method is disclosed for measuring semiconductor devices for certain parameters and placing specific devices into different categories or “bins” according to the measured parameters. Measurable parameters include performance/speed-grading, power consumption, current leakage, and the ability to operate at certain temperature extremes. A method for speed grading semi-custom ASIC devices is specifically described that does not require removing partially completed wafers from the fab line for testing. To speed-grade a new boat of partially completed un-customized wafers, a small number of wafers (1 or 2) are processed to completion while being customized specifically for a customer design requiring only the slowest bin. These wafer(s) are then performance tested and the remaining wafers in the boat are certified according to these results for their performance level and placed in a wafer bank for later use.

Abstract: A solution for answering a call on a mobile phone is described including a “courtesy answering mode”. Here, the receiving party manually activates a recorded or automatically constructed message to be played for the caller, indicating to the calling party in effect that the receiving party will take their call shortly, and/or is relocating to a location where they will be able to properly receive the call. The receiving party can then move in a quiet and unhurried manner, without feeling compelled to start talking to the calling party. When the receiving party reaches the appropriate location, they will activate the phone to initiate the conversation. In addition, various remote controller/communicator accessories are described to further aid in answering or processing an incoming call in a manner courteous to those in close proximity to the receiving party.

Abstract: An enhanced communication and voicemail solution for mobile phones is described where still images and/or video clips are injected into the voice stream creating a “video-voice” call. When a receiving party is not available to take a video-voice call, this combined stream of voice and image information is stored at the mobile service provider in a manner similar to voice mail today. Then, stored video-voicemails may be retrieved at a later time by the receiving party. Also, realtime video-voice conversations may be recorded for later retrieval in order to document the conversation or because a party in the conversation is not able to view the images realtime. While the sending party may use a normal size mobile phone containing a miniature digital camera, the receiving party may view video-voicemail images on a variety of devices including a wireless mobile phone or PDA, or alternately a conventional PC connected to the World Wide Web.

Abstract: To serve prototype and initial production requirements, an emulation solution is described where an ASIC semiconductor device die containing primarily fixed functions, for example a DSP processor with programmable instruction interface, is mounted in the same package as a conventional FPGA device—the FPGA in this example implementing custom instructions for DSP algorithm acceleration and connecting primarily to the fixed function device. A fully integrated, single die ASIC solution is then available for migration of designs to higher volume production where some of the field programmable function will be replaced with fixed function. The base wafer for the ASIC device used in the prototype package and base wafer for the volume production ASIC device may be the same.

Abstract: A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.

Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

Abstract: A system is described where the existing proliferation of standard electrical junction boxes in a typical home or building implement a form of “Bio-Feedback for Home Energy”, increasing user awareness and enabling more effective and efficient energy usage. Energy-related information is gathered by way of EMAC (Energy Monitoring And Control) points typically installed at standard electrical junction boxes used for power plug receptacles and wall switches. In addition to being visually displayed at the point of energy use or measurement, energy-related information—electrical and thermal—is typically communicated through a powerline or wireless data link to a centrally located intelligent device where it is monitored, analyzed, profiled, viewed, and also used for energy-related control functions. Energy consumption can be alternately displayed in terms of cost-per-time. Energy monitoring may be also added at the electrical breaker box to supplement distributed EMAC points.

Abstract: A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.

Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

Abstract: A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC. Other embodiments allow a determination to be made of the ideal number of custom mask steps, taking into consideration performance, cost, time, and routability.

Abstract: A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.

Abstract: On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die region. Such stored information may include a circuit design identifier or a proprietary technology identifier. Such identifiers minimize IC confusion and aid in tracking usage of proprietary technology.

Abstract: A gate array integrated circuit wafer is formed having M−N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M−N generic metal interconnection layers. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer.

Abstract: A new circuit architecture is provided for testing digital integrated circuits which allows one to arbitrarily force any combination of logic values to be simultaneously driven onto any combination of internal nets. This allows all of the connections to each internal logic cell, and the logic cell itself, to be verified by applying a set of test patterns to each logic cell individually. In this way, the integrity of the entire device can be verified without having knowledge of the operation of the circuit as a whole.