Abstract: A new circuit architecture is provided for testing digital integrated circuits which allows one to arbitrarily force any combination of logic values to be simultaneously driven onto any combination of internal nets. This allows all of the connections to each internal logic cell, and the logic cell itself, to be verified by applying a set of test patterns to each logic cell individually. In this way, the integrity of the entire device can be verified without having knowledge of the operation of the circuit as a whole.

Abstract: A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer's performance and/or yield requirements.

Abstract: A new circuit architecture is provided for testing digital integrated circuits which allows one to arbitrarily force any combination of logic values to be simultaneously driven onto any combination of internal nets. This allows all of the connections to each internal logic cell, and the logic cell itself, to be verified by applying a set of test patterns to each logic cell individually. In this way, the integrity of the entire device can be verified without having knowledge of the operation of the circuit as a whole.

Abstract: A device-under-test card includes a matrix of fuses and/or antifuses formed as part of a multi-layered structure. The matrix of fuses and/or antifuses can be electrically programmed to connect any one of first electrical contacts to any one of second electrical contacts and so allows the device-under-test card to act as a junction between burn-in board traces couplable to signal drivers and/or receivers and burn-in board traces couplable to terminals of a device-under-test. The device-under-test card also includes a discrete resistor or alternatively a resistor ladder that permits a terminal of a device-under-test to be coupled to a power or ground terminal or to any combination of resistances including a short, in addition or as an alternative to any one of various signal drivers and/or receivers.

Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customized pattern of bonding pads is then formed over the one or both surfaces of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalized pattern of bonding pads may also be formed on the surfaces of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearby via.

Abstract: The invention provides a multi-stage architecture where the first stage is extremely wide and fast, but has a shallow depth which greatly reduces cost. A second stage provides a more conventional variable width/depth memory. Between the two stages is a programmable cross point switch matrix which determines which channels, of the many channels from the first stage, is to be connected as inputs to the second stage. Trigger comparisons may be performed in either or both stages.

Abstract: A programmable interconnect system includes a two-level hierarchal structure of programmable interconnect chips on a circuit board. The first-level, or "local", interconnect chips are connected to user components. A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.

Abstract: A printed circuit board includes an array of conductive pads including component-mounting holes disposed on first and second surfaces thereon. An array of conductive attachment lands arranged in pairs of first and second attachment lands are disposed on the first and second surfaces. The first and second attachment lands are insulated from one another and separated by a distance selected to allow attachment of standard sized components therebetween on the first and second surfaces of said circuit board. First and second conductive power distribution planes are disposed on the first and second surfaces and are insulated from the conductive pads and the second attachment lands disposed thereon.

Abstract: A package for one or more integrated circuit dice which includes a spreader which provides a conventional signal path between the die and a printed circuit board to which it is demountably attached as well as an additional, more readily accessible subset of signals, preferably available through a flexible cable extending horizontally from the package. The spreader provides a first set of contacts on a first side for interface to the integrated circuit dice, a second set of contacts on a second side opposite the first side which are connected to some of the contacts of the first set of contacts for connection to the printed circuit board, and a third set of contacts on the first side along one edge thereof for engaging the flexible cable and carrying the subset of signals.

Abstract: A phase decoding technique is provided which, when applied to a pair of quadrature-phased digital-electronic signals (i.e. having a 90.degree. phase relationship) such as those normally associated with incremental optical position encoders, produces signals suitable for incrementing or decrementing up-down counters in accordance with the phase relationship and pulse rate of these quadrature phased signals. This is accomplished through circuitry which is entirely of a digital nature and relys on comparisons of samples of the quadrature-phased signals which are taken and stored in a time-sequential manner. Since no analog circuitry is employed, the disadvantages of phase decoders using prior art techniques are avoided.

Abstract: An absolute encoding system is provided based on an incremental optical encoder which, together with a low power circuit technology and means for pulsing the light emitter(s) of the encoder (normally the largest power consuming device(s) in such a system) with a signal of low duty cycle and means for sampling the light detector outputs during the appropriate period of response to the emitted light pulses, produces an encoder system having extremely low internal power consumption allowing not only data retention but also data acquisition during periods of isolation from an external power supply by relying on its own relatively small battery-based power source.

Abstract: A sound track selector system for a phonograph record player is provided comprising a light emitter and light detecting sensor carried beneath a sound stylus pick-up arm, directing light to the face of a phonograph record and receiving reflected light along axes substantially perpendicular to the record face and substantially parallel to one another as the emitter and sensor scan the record, means connected to the sensor for determining the bands between recorded sound in response to reflected light, and means for controlling the position of the pickup arm in response to preselected portions of the recording in relation to the detection of the unrecorded portions of the record. An optical encoder system is also provided for detecting the peripheral positions of the pickup arm with respect to the phonograph record.