Patents by Inventor Robert P. Adler
Robert P. Adler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11686767Abstract: In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.Type: GrantFiled: November 2, 2017Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert P. Adler, R. Selvakumar Raja Gopal
-
Patent number: 11372674Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: October 27, 2020Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Robert P. Adler, Robert De Gruijl, Sridhar Lakshmanamurthy, Ramadass Nagarajan, Peter J. Elardo
-
Patent number: 11105854Abstract: In one embodiment, an apparatus includes multiple die and at least one interconnect to couple the die. A first die includes one or more cores, a first fabric and a first fabric transactor coupled to the first fabric, the first fabric transactor to initiate a functional test of the apparatus in response to a test signal, cause at least one first test transaction to be sent to a second die, receive a first response to the at least one first test transaction from the second die, and identify, based at least in part on the first response to the at least one test transaction, a location of a failure and report the location of the failure to a destination. Other embodiments are described and claimed.Type: GrantFiled: November 2, 2017Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert P. Adler, Ki Yoon
-
Patent number: 11100023Abstract: In one example, a semiconductor die includes a plurality of agents and a fabric coupled to at least some of the plurality of agents. The fabric may include at least one router to provide communication between two or more of the plurality of agents, the at least one router coupled to a first agent of the plurality of agents, where the first agent is to send a first message to the at least one router, the first message comprising a first header including a first source identifier, and the at least one router is to validate that the first source identifier is associated with the first agent and if so to direct the first message towards a destination agent, and otherwise to prevent the first message from being directed towards the destination agent. Other embodiments are described and claimed.Type: GrantFiled: September 28, 2017Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Ruirui Huang, Nilanjan Palit, Robert P. Adler, Ioannis T. Schoinas, Avishay Snir, Boris Dolgunov
-
Patent number: 10936048Abstract: In one embodiment, an apparatus includes a bulk write circuit to generate a bulk write message to send to a destination agent to cause the destination agent to write data comprising register contents into a plurality of registers, at least some of the plurality of registers comprising non-consecutive registers. The bulk write message may include a first message header, a first chunk header including an address of a first register of a first subset of the plurality of registers, and a first payload portion having the register contents for the first subset of the plurality of registers. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2019Date of Patent: March 2, 2021Assignee: Intel CorporationInventors: Ben Furman, Yoni Aizik, Robert P. Adler, Robert Hesse, Chen Ranel
-
Publication number: 20210042147Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.Type: ApplicationFiled: October 27, 2020Publication date: February 11, 2021Inventors: Robert P. Adler, Robert De Gruijl, Sridhar Lakshmanamurthy, Ramadass Nagarajan, Peter J. Elardo
-
Patent number: 10911261Abstract: In an embodiment, a system on chip includes: a plurality of local networks having one or more local endpoints and a first router, where at least some of the one or more local endpoints of different local networks have non-unique port identifiers; at least one global network having one or more global endpoints and at least one second router, where the one or more global endpoints have unique port identifiers; and a plurality of transparent bridges to couple between one of the plurality of local networks and the at least one global network. Other embodiments are described and claimed.Type: GrantFiled: December 19, 2016Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Robert P. Adler, Lichen Weng, Christopher C. Gianos
-
Patent number: 10860762Abstract: Methods and apparatus relating to subsystem-based System on Chip (SoC) integration are described. In one embodiment, logic circuitry determines one or more components of a subsystem. The subsystem supports an architectural feature to be implemented on a System on Chip (SoC) device. A first interface communicatively couples a first component of the subsystem to a first component of another subsystem. A second interface communicatively couples at least one component of the subsystem to at least one chassis component of the SoC device or communicatively couples the at least one component of the subsystem to at least one non-chassis component of the other subsystem. In an embodiment, components of the subsystem may be packaged such that the packaging generates a reusable collateral that allows for fast integration of all aspects of design in any SoC device with a compatible chassis prior to manufacture.Type: GrantFiled: July 11, 2019Date of Patent: December 8, 2020Assignee: Intel CorprationInventors: Robert P. Adler, Husnara Khan, Satish Venkatesan, Ramamurthy Sunder, Mukesh K. Mishra, Bindu Lalitha, Hassan M. Shehab, Sandhya Seshadri, Dhrubajyoti Kalita, Wendy Liu, Hanumanth Bollineni, Snehal Kharkar
-
Patent number: 10846126Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: December 28, 2016Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Robert P. Adler, Robert De Gruijl, Sridhar Lakshmanamurthy, Ramadass Nagarajan, Peter J. Elardo
-
Publication number: 20190340313Abstract: Methods and apparatus relating to subsystem-based System on Chip (SoC) integration are described. In one embodiment, logic circuitry determines one or more components of a subsystem. The subsystem supports an architectural feature to be implemented on a System on Chip (SoC) device. A first interface communicatively couples a first component of the subsystem to a first component of another subsystem. A second interface communicatively couples at least one component of the subsystem to at least one chassis component of the SoC device or communicatively couples the at least one component of the subsystem to at least one non-chassis component of the other subsystem. In an embodiment, components of the subsystem may be packaged such that the packaging generates a reusable collateral that allows for fast integration of all aspects of design in any SoC device with a compatible chassis prior to manufacture.Type: ApplicationFiled: July 11, 2019Publication date: November 7, 2019Applicant: Intel CorporationInventors: Robert P. Adler, Husnara Khan, Satish Venkatesan, Ramamurthy Sunder, Mukesh K. Mishra, Bindu Lalitha, Hassan M. Shehab, Sandhya Seshadri, Dhrubajyoti Kalita, Wendy Liu, Hanumanth Bollineni, Snehal Kharkar
-
Publication number: 20190286223Abstract: In one embodiment, an apparatus includes a bulk write circuit to generate a bulk write message to send to a destination agent to cause the destination agent to write data comprising register contents into a plurality of registers, at least some of the plurality of registers comprising non-consecutive registers. The bulk write message may include a first message header, a first chunk header including an address of a first register of a first subset of the plurality of registers, and a first payload portion having the register contents for the first subset of the plurality of registers. Other embodiments are described and claimed.Type: ApplicationFiled: March 29, 2019Publication date: September 19, 2019Inventors: Ben Furman, Yoni Aizik, Robert P. Adler, Robert Hesse, Chen Ranel
-
Patent number: 10255399Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.Type: GrantFiled: October 31, 2016Date of Patent: April 9, 2019Assignee: Intel CorporationInventors: Krishnan Srinivasan, Robert P. Adler, Eric A. Geisler, Robert De Gruijl, Jay Tomlinson
-
Publication number: 20190095372Abstract: In one example, a semiconductor die includes a plurality of agents and a fabric coupled to at least some of the plurality of agents. The fabric may include at least one router to provide communication between two or more of the plurality of agents, the at least one router coupled to a first agent of the plurality of agents, where the first agent is to send a first message to the at least one router, the first message comprising a first header including a first source identifier, and the at least one router is to validate that the first source identifier is associated with the first agent and if so to direct the first message towards a destination agent, and otherwise to prevent the first message from being directed towards the destination agent. Other embodiments are described and claimed.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Ruirui Huang, Nilanjan Palit, Robert P. Adler, Ioannis T. Schoinas, Avishay Snir, Boris Dolgunov
-
Patent number: 10235486Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.Type: GrantFiled: September 29, 2016Date of Patent: March 19, 2019Assignee: Intel CorporationInventors: Krishnan Srinivasan, Robert P. Adler, Robert De Gruijl, Jay Tomlinson, Eric A. Geisler
-
Publication number: 20190033367Abstract: In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.Type: ApplicationFiled: November 2, 2017Publication date: January 31, 2019Inventors: Lakshminarayana Pappu, Robert P. Adler, R. Selvakumar Raja Gopal
-
Publication number: 20190033368Abstract: In one embodiment, an apparatus includes multiple die and at least one interconnect to couple the die. A first die includes one or more cores, a first fabric and a first fabric transactor coupled to the first fabric, the first fabric transactor to initiate a functional test of the apparatus in response to a test signal, cause at least one first test transaction to be sent to a second die, receive a first response to the at least one first test transaction from the second die, and identify, based at least in part on the first response to the at least one test transaction, a location of a failure and report the location of the failure to a destination. Other embodiments are described and claimed.Type: ApplicationFiled: November 2, 2017Publication date: January 31, 2019Inventors: Lakshminarayana Pappu, Robert P. Adler, Ki Yoon
-
Patent number: 10164880Abstract: In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.Type: GrantFiled: November 14, 2014Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit R. Verma, Robert P. Adler
-
Patent number: 10042729Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.Type: GrantFiled: April 1, 2016Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert De Gruijl, Suketu U. Bhatt, Robert P. Adler, R Selvakumar Raja Gopal, Rius Tanadi
-
Publication number: 20180181432Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: Robert P. Adler, Robert De Gruijl, Sridhar Lakshmanamurthy, Ramadass Nagarajan, Peter J. Elardo
-
Publication number: 20180176118Abstract: In an embodiment, a system on chip includes: a plurality of local networks having one or more local endpoints and a first router, where at least some of the one or more local endpoints of different local networks have non-unique port identifiers; at least one global network having one or more global endpoints and at least one second router, where the one or more global endpoints have unique port identifiers; and a plurality of transparent bridges to couple between one of the plurality of local networks and the at least one global network. Other embodiments are described and claimed.Type: ApplicationFiled: December 19, 2016Publication date: June 21, 2018Inventors: Robert P. Adler, Lichen Weng, Christopher C. Gianos