Patents by Inventor Robert P. Adler
Robert P. Adler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180121574Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.Type: ApplicationFiled: October 31, 2016Publication date: May 3, 2018Inventors: Krishnan Srinivasan, Robert P. Adler, Eric A. Geisler, Robert De Gruijl, Jay Tomlinson
-
Patent number: 9954792Abstract: Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.Type: GrantFiled: December 20, 2014Date of Patent: April 24, 2018Assignee: Intel CorporationInventors: Kevin B. Theobald, Rupin H. Vakharwala, Robert J. Toepfer, Erik G. Hallnor, Robert P. Adler
-
Publication number: 20180089342Abstract: In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2016Publication date: March 29, 2018Inventors: Krishnan Srinivasan, Robert P. Adler, Robert De Gruijl, Jay Tomlinson, Eric A. Geisler
-
Publication number: 20180060473Abstract: A topology metadata file is identified that describes a topology of a system on chip (SoC) to be created, where the topology includes a plurality of computing blocks to be interconnected by a fabric. A corresponding computing block metadata file is identified for each of the plurality of computing blocks, where each of the computing block metadata files is to describe attributes of the corresponding computing block. The topology metadata file and the computing block metadata files are parsed to identify configuration attributes of the SoC. An intermediate representation of the SoC is generated based on the configuration attributes.Type: ApplicationFiled: August 7, 2017Publication date: March 1, 2018Applicant: Intel CorporationInventor: Robert P. Adler
-
Patent number: 9891282Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.Type: GrantFiled: December 24, 2015Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert P. Adler, Suketu U. Bhatt, Robert De Gruijl, Kah Meng Yeem
-
Patent number: 9853916Abstract: Described is an apparatus comprising one or more router circuitries. One or more of the circuitries may be a shared-bus router circuitry including a plurality of shared-bus ports and a shared-bus datapath, and one or more of the circuitries may be a crossbar router circuitry including a plurality of crossbar ports and a crossbar datapath. Also described are methods of making the apparatus, which may include: providing one or more design files modeling the apparatus, the shared-bus datapath, and the crossbar datapath; incorporating a configuration parameter for the datapath into the one or more design files; and setting an RTL configuration parameter to instantiate either the shared-bus backbone or the crossbar backbone. The methods may also include loading the one or more design files with a design tool and compiling the one or more design files with the design tool.Type: GrantFiled: April 1, 2016Date of Patent: December 26, 2017Assignee: Intel CorporationInventors: Robert P. Adler, Cristian E. Savin, Vishnu Vardhan Nandakumar, Yashpreet Kaur, Soe Myint
-
Publication number: 20170289063Abstract: Described is an apparatus comprising one or more router circuitries. One or more of the circuitries may be a shared-bus router circuitry including a plurality of shared-bus ports and a shared-bus datapath, and one or more of the circuitries may be a crossbar router circuitry including a plurality of crossbar ports and a crossbar datapath. Also described are methods of making the apparatus, which may include: providing one or more design files modeling the apparatus, the shared-bus datapath, and the crossbar datapath; incorporating a configuration parameter for the datapath into the one or more design files; and setting an RTL configuration parameter to instantiate either the shared-bus backbone or the crossbar backbone. The methods may also include loading the one or more design files with a design tool and compiling the one or more design files with the design tool.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Robert P. Adler, Cristian E. Savin, Vishnu Vardhan Nandakumar, Yashpreet Kaur, Soe Myint
-
Publication number: 20170286247Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: LAKSHMINARAYANA PAPPU, ROBERT DE GRUIJL, SUKETU U. BHATT, ROBERT P. ADLER, R SELVAKUMAR RAJA GOPAL, RIUS TANADI
-
Patent number: 9753875Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: January 20, 2016Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
-
Patent number: 9727679Abstract: A topology metadata file is identified that describes a topology of a system on chip (SoC) to be created, where the topology includes a plurality of computing blocks to be interconnected by a fabric. A corresponding computing block metadata file is identified for each of the plurality of computing blocks, where each of the computing block metadata files is to describe attributes of the corresponding computing block. The topology metadata file and the computing block metadata files are parsed to identify configuration attributes of the SoC. An intermediate representation of the SoC is generated based on the configuration attributes.Type: GrantFiled: December 20, 2014Date of Patent: August 8, 2017Assignee: Intel CorporationInventor: Robert P. Adler
-
Publication number: 20170184666Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Inventors: Lakshminarayana Pappu, Robert P. Adler, Suketu U. Bhatt, Robert De Gruijl, Kah Meng Yeem
-
Patent number: 9658978Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.Type: GrantFiled: March 13, 2014Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray, Robert P. Adler
-
Patent number: 9602237Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.Type: GrantFiled: December 19, 2014Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Robert P. Adler, Geetani R. Edirisooriya, Joseph Murray, Deep K. Buch
-
Publication number: 20160182391Abstract: Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.Type: ApplicationFiled: December 20, 2014Publication date: June 23, 2016Inventors: Kevin B. Theobald, Rupin H. Vakharwala, Robert J. Toepfer, Erik G. Hallnor, Robert P. Adler
-
Publication number: 20160179161Abstract: For each of a plurality of ports to be defined for an interconnect fabric, a respective computing block is identified to be connected to the port. One or more entries in a library of decode information is identified for each of the identified computing blocks. An intermediate representation of a fabric of the system on chip is generated based on the identified entries in the library of decode information.Type: ApplicationFiled: December 22, 2014Publication date: June 23, 2016Inventors: Robert P. Adler, Satish Venkatesan, Timothy J. Jennings
-
Publication number: 20160180001Abstract: A topology metadata file is identified that describes a topology of a system on chip (SoC) to be created, where the topology includes a plurality of computing blocks to be interconnected by a fabric. A corresponding computing block metadata file is identified for each of the plurality of computing blocks, where each of the computing block metadata files is to describe attributes of the corresponding computing block. The topology metadata file and the computing block metadata files are parsed to identify configuration attributes of the SoC. An intermediate representation of the SoC is generated based on the configuration attributes.Type: ApplicationFiled: December 20, 2014Publication date: June 23, 2016Inventor: Robert P. Adler
-
Publication number: 20160182186Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Robert P. Adler, Geetani R. Edirisooriya, Joseph Murray, Deep K. Buch
-
Publication number: 20160132447Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: ApplicationFiled: January 20, 2016Publication date: May 12, 2016Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
-
Patent number: 9270576Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: March 13, 2014Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
-
Patent number: 9213666Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.Type: GrantFiled: September 26, 2014Date of Patent: December 15, 2015Assignee: Intel CorporationInventors: Robert P. Adler, Eran Tamari, Mikal C. Hunsaker, Sridhar Lakshmanamurthy, Michael T. Klinglesmith, Blaise Fanning