Abstract: Multiple channels are aggregated. In an example embodiment, first data is transmitted on a first channel to a wireless device, and second data is simultaneously transmitted on a second channel to the wireless device. The first data and the second data are transmitted in a coordinated manner by aggregating the first channel and the second channel. Various example channel characteristics and combinations thereof are described. Different data allocation options for aggregated channels are described. Other alternative implementations are also presented herein.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: Multiple channels are aggregated. In an example embodiment, first data is transmitted on a first channel to a wireless device, and second data is simultaneously transmitted on a second channel to the wireless device. The first data and the second data are transmitted in a coordinated manner by aggregating the first channel and the second channel. Various example channel characteristics and combinations thereof are described. Different data allocation options for aggregated channels are described. Other alternative implementations are also presented herein.

Abstract: Multiple channels are aggregated. In an example embodiment, first data is transmitted on a first channel to a wireless device, and second data is simultaneously transmitted on a second channel to the wireless device. The first data and the second data are transmitted in a coordinated manner by aggregating the first channel and the second channel. Various example channel characteristics and combinations thereof are described. Different data allocation options for aggregated channels are described. Other alternative implementations are also presented herein.

Abstract: High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.

Abstract: Multiple channels are aggregated. In an example embodiment, first data is transmitted on a first channel to a wireless device, and second data is simultaneously transmitted on a second channel to the wireless device. The first data and the second data are transmitted in a coordinated manner by aggregating the first channel and the second channel. Various example channel characteristics and combinations thereof are described. Different data allocation options for aggregated channels are described. Other alternative implementations are also presented herein.

Abstract: Multiple channels are aggregated. In an example embodiment, first data is transmitted on a first channel to a wireless device, and second data is simultaneously transmitted on a second channel to the wireless device. The first data and the second data are transmitted in a coordinated manner by aggregating the first channel and the second channel. Various example channel characteristics and combinations thereof are described. Different data allocation options for aggregated channels are described. Other alternative implementations are also presented herein.

Abstract: A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue.

Abstract: Multiple channels are aggregated. In an example embodiment, first data is transmitted on a first channel to a wireless device, and second data is simultaneously transmitted on a second channel to the wireless device. The first data and the second data are transmitted in a coordinated manner by aggregating the first channel and the second channel. Various example channel characteristics and combinations thereof are described. Different data allocation options for aggregated channels are described. Other alternative implementations are also presented herein.

Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Abstract: In a particular embodiment, a system includes a controller configured to receive proximity data associated with a first device of a plurality of devices. The proximity data indicates a relative location of each of one or more devices of the plurality of devices with respect to the first device. The controller is further configured to determine an estimated intermodulation product. The estimated intermodulation product is calculated based on the proximity data. The controller is further configured to initiate transmission of one or more commands, based on the estimated intermodulation product, to at least one device of the plurality of devices.

Abstract: A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue.

Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Abstract: Techniques for designing a communications unit including a signal separation module for energy harvesting. In an exemplary aspect, the signal separation module includes first and second quadrature hybrids coupled by band-pass filters (BPF's). Incoming signals within the pass-band of the BPF's are directed through the quadrature hybrids and through the BPF's, and emerge as a desired pass-band signal to be processed by an RX processing module. Incoming signals lying outside the pass-band of the BPF's are reflected from the BPF's back to the first quadrature hybrid, and output as a non-pass-band signal to be processed by an energy harvesting module. In a further exemplary aspect, the signal separation module resides in a detachable module coupleable to a wireless communications device, and a signal transmitted by the wireless communications device is coupled to the signal separation module for energy harvesting.

Abstract: Multiple channels are aggregated. In an example embodiment, first data is transmitted on a first channel to a wireless device, and second data is simultaneously transmitted on a second channel to the wireless device. The first data and the second data are transmitted in a coordinated manner by aggregating the first channel and the second channel. Various example channel characteristics and combinations thereof are described. Different data allocation options for aggregated channels are described. Other alternative implementations are also presented herein.

Abstract: High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.

Abstract: Multiple channels are aggregated. In an example embodiment, first data is transmitted on a first channel to a wireless device, and second data is simultaneously transmitted on a second channel to the wireless device. The first data and the second data are transmitted in a coordinated manner by aggregating the first channel and the second channel. Various example channel characteristics and combinations thereof are described. Different data allocation options for aggregated channels are described. Other alternative implementations are also presented herein.