Abstract: A digital/analog hybrid frequency synthesizer having a digital frequency synthesizer for digitally generating an analog output signal of a predetermined frequency within a frequency range of f to f+.DELTA.f; an input stage analog frequency synthesizer for, receiving the digital frequency synthesizer output signal and I analog input stage input signals, each input stage input signal separated in frequency from a next one by a frequency increment of .DELTA.f wherein a first one and a last one of the input stage input signals are respectively of a frequency of f.sub.A and f.sub.A +(I-1).DELTA.

Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered and amplitude limited to reduce spurious noise. In one embodiment, the DDS frequency synthesizer is coupled to a phase lock loop which receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size.

Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to drive a phase lock loop. The DDS generates a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. A phase lock loop receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal.In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size.