Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.

Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.

Abstract: An on-chip clock distribution system and method which utilizes local clock buffers to provide an improved clock signal distribution while avoiding the disadvantages of conventional central buffer and repowered distribution systems. The system also reduces distribution routing problems and distributes “delta-I” problem and thermal problem, and also supports better local delay tuning.

Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.

Abstract: A method for building a multiprocessor data processing system is disclosed. A component among a collection of components on a multichip module is identified. The collection of components, which includes both processors and cache components, and each of the components may be functional or non-functional. A determination is made as to whether or not the identified component is functional. In response to a determination that the identified component is functional, the process of component association is performed between the identified component and other functional components on the multichip module such that interconnect length between all functional components can be minimized.

Abstract: A dynamic logic circuit is implemented which decouples the reset of the output from the reset of the evaluation node. An N-tree logic circuit generates a logical output signal in response to a first set of input signals. The output signal is coupled to a gate of a first n-type field effect transistor (NFET) of a parallel coupled pair of NFET devices. The parallel drains are coupled to an output of the dynamic logic circuit and the parallel sources are coupled to ground. The gate of the second NFET device of the pair is coupled to the junction of a source and drain, respectively, of a series connected p-type field effect transistor (PFET) device, and a third NFET device. The third NFET device has a source coupled to ground, and the PFET device has a drain coupled to a voltage supply. Gates of the PFET device and the third NFET device are connected together and receive a logic signal whereby the output of the dynamic logic circuit may be reset.

Abstract: An anti-charge share device and method for operation ensure that charge share protection is provided for nodes in a logic circuit during an evaluate stage with low costs in terms of power and circuit performance. The anti-charge sharing device includes a transistor coupled between pre-charge node and a second node being evaluated. By coupling the charge share device between the pre-charge node and the node to be evaluated, operation of the charge share device is dependent upon a node which no longer requires a charge-sharing protection.

Abstract: A system and method for increasing the gain per stage and signal edge transition speed, as well as the edge phase accuracy of an input signal. In an exemplary embodiment, a distributed clock signal is produced by an enhanced clock buffer circuit which includes additional weighted static gain chains connected within the buffer circuit. The buffer circuit retains the benefits of the split-drive, dual output transistor configuration, and also substantially improves circuit gain per delay gate by connecting the weighted static gain chains between pulse generators and output transistors of the buffer circuit. The gain chains are designed to rapidly propagate the edge that fires their respective output transistors but slowly propagate the edge that turns the output transistor off, by reducing the devices that propagate the shut-off transition. N-type and p-type devices within the buffer circuit are arranged and sized to promote the gain characteristic of the split drive buffer circuit.

Abstract: One or more redundant sub-arrays (324) are added to a memory (316-322) of a data processing system (300) to allow a manufacturer to compensate for defects introduced during the fabrication phase of a semiconductor device upon which it is implemented. Each of these redundant sub-arrays includes a separate and independent wordline decoder (202), bitline decoder (206), and input/output circuit (208). Furthermore, the memory to which the redundant sub-array is added is typically an on-chip memory which is organized into bit-slice sub-arrays. The bit-slice organization of the memory allows the redundant sub-array to be chained together with the on-chip memory. Data-in/data-out multiplexers are used to steer bit-slices of the data around the defective sub-arrays.

Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.

Abstract: A method and apparatus are provided for generating synchronized clock signals. According to the method and apparatus, first and second pluralities of signals are generated, having time-varying phase differences with respect to a reference clock. The first clock is supplied by a succession of signals from among the first plurality of signals, in which one of the signals succeeds another responsive to a first phase difference. The second clock is supplied by a second succession of signals from among the second plurality of signals. One signal in the second succession of signals succeeds another responsive to a second phase difference. The succession among the first plurality of signals is also responsive to the second phase difference.

Abstract: A CMOS differential amplifier uses a first pair of complementary MOSFETs and a second pair of complementary MOSFETs coupled to a power supply (by another pair of MOSFETs) in such a manner as to be self-biasing and have improved channel-length modulation characteristics. An N-type MOSFET couples the first and second complementary MOSFET pairs to ground potential via a first resistor, and a P-type MOSFET couples the first and second complementary MOSFET pairs to a power-supply via a second resistor. The first and second resistors can be provided using non-salicided N-type MOSFET resistors. The third N-type MOSFET preferably has a low-threshold voltage, including a zero-threshold voltage, and the substrates of the P-type MOSFETs in the first and second complementary pairs are further preferably connected to the sources of those MOSFETs in order to reduce body-sensitivity effects.

Abstract: A system and method according to the present invention for mapping a clocking scheme to determine robust clocking schemes in a logic circuit is disclosed. The circuit can be represented by a clocking graph, the clocking graph having at least one loop including a plurality of vertices, wherein two vertices represent each relevant signal, one for a rising edge and one for a falling edge. Additionally, a plurality of constraints of the logic circuit propagate through circuit delays.

Abstract: A method and implementing structures for a domino block circuit configuration includes a plurality of domino logic blocks including inverter circuits to provide inverted signals which are needed for a comprehensive logic analysis and processing. A plurality of clocking signals are applied at various clocking inputs throughout the circuit. The clocking signals are timed relative to each other in a timing sequence to assure that the logic circuit evaluations occur only after relevant data and switching signals have stabilized.

Abstract: A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit. The clock generation apparatus includes a device which generates a reference frequency, an acoustic wave oscillator having an oscillation frequency slightly faster than the reference frequency and a circuit configuration coupled to the acoustic wave oscillator which generates frequency bearing signals in response to an output of the acoustic wave oscillator. The frequency bearing signals carry negligible jitter. The circuit configuration includes a quadrature rotator for controlling clock phase, a clock distributor for efficiently dispersing clock signals to the microprocessor integrated circuit, a bus divider which provides a feedback clock signal phase aligned with the reference frequency, a phase detector for detecting the phase difference of a bus clock signal and the feedback clock signal, and a digital filter responsive to the phase detector.

Abstract: A time interval division circuit that generates a delayed signal that is a precise integer fraction of the clock cycle. A digital delay loop including a digital delay line is locked to the clock cycle and controls a second digital delay line. The delay line characteristics determine the fraction of the clock cycle generated. The time interval division circuit tracks the clock cycle, rather than on-chip circuit delays as conventional delay lines.

Abstract: A cache sub-array method and apparatus for use in microprocessor integrated circuits. A processor unit is disposed within a central region of the microprocessor integrated circuit; a peripheral region is designated as a cache memory array region and surrounds the central region; a predetermined number of cache memory sub-arrays are placed in the peripheral region such that variable size cache memory arrays may be efficiently created. The cache memory sub-arrays contain a fixed fraction of a total cache word. The microprocessor integrated circuit itself has a modular cache memory array of variable size, and includes a central region having a processor unit disposed therein, a peripheral region designated as a cache memory array region surrounding the central region, and a predetermined number of cache memory sub-arrays disposed in the peripheral region such that the cache memory sub-arrays compose a modular cache memory array of variable size.

Abstract: A system and method for replacing sense amplifiers used in conventional RAMS with domino circuits in order to create a domino static random access memory. The domino SRAM of the present invention is created through extensive partitioning of conventional bit lines into local bit lines corresponding to the local cell groups within the SRAM. A ratioed inverter is coupled to each one of the local bit lines in a local cell group to form dynamic nodes and to provide a sense function for the local cell group. A tree-hierarchy of Or-gates is coupled to the ratioed inverters to complete the domino circuit.

Abstract: A clock edge regulator that adds precision midcycle edge timing to an existing clock distribution. Two phase detector and phase delay pairs regulate the rising and falling clock edges. The falling edge is regulated to a precision time interval division of the clock period to provide an accurate duty cycle for the clock distribution.

Abstract: A system and method is disclosed for increasing read performance of domino SRAMS. A conventional word-line, which drives two transistors per cell, is replaced with two separate word-lines. The first word-line drives one transistor and the second word-line drives the other transistor. The first word-line is used to write zeros into cells, while the second word line is used to both write ones into cells and to read the contents of the cells. Since the second word-line drives only one transistor during read operations, one-half of the gate load on the writeead word-line is eliminated.