Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

Abstract: An semiconductor structure, method of fabrication therefor, and design structure therefor is provided. A thermal grid is formed over at least a portion of a substrate. An insulating layer is formed over at least a portion of the thermal grid. A resistor is formed over at least a portion of the insulating layer. A buried interconnect is connected to the thermal grid via at least one contact. The buried interconnect is adapted to receive thermal energy from the thermal grid via the at least one contact.

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

Abstract: After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.

Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

Abstract: After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.

Abstract: Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.

Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

Abstract: A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.

Abstract: Disclosed is a semiconductor-on-insulator (SOI) structure (e.g., an SOI field effect transistor (FET)) and method of forming the SOI structure so as to have sub-insulator layer void(s) selectively placed so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device and the second section may contain a second device. Alternatively, the first and second sections may comprise different regions of the same device. For example, in an SOI FET, sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.

Abstract: An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.

Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

Abstract: A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.

Abstract: Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.

Abstract: An integrated circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; an insulation layer over the substrate; a resistor over the insulation layer; a thermal gate over the resistor; and a heat sink connected to the thermal gate via a substrate contact, the heat sink adapted to receive thermal energy from the resistor via the thermal gate.

Abstract: A circuit for testing a floating body field-effect transistor (FET), and a related method, are provided. Embodiments of this invention include a circuit including a contacted-body FET structure that can be operated in a floating body mode or a body-contacted mode, and a passgate FET. A body of the contacted-body FET structure is connected to the drain of the passgate FET. Voltage can be applied to the passgate FET to either allow or restrict current flow through the passgate FET, to operate the contacted-body FET structure in body contacted mode or floating body mode. Data can be taken in each mode and compared to extract a floating body voltage.

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.