Patents by Inventor Robert Starkston
Robert Starkston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180350737Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: June 7, 2018Publication date: December 6, 2018Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
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Publication number: 20180343744Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.Type: ApplicationFiled: December 3, 2015Publication date: November 29, 2018Applicant: INTEL CORPORATIONInventors: Robert Starkston, Richard C. Stamey, Robert L. Sankman, Scott M. Mokler
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Patent number: 10125013Abstract: Apparatuses, systems, and methods associated with placement of magnets within a microelectromechanical system device are disclosed herein. In embodiments, a method of affixing at least one magnet in a microelectromechanical system, may include affixing an electromagnetic actuator to a base structure of the microelectromechanical system, the affixing including affixing the electromagnetic actuator within a recess formed in the base structure. The method may further include placing a magnet within the recess, wherein the recess includes at least a portion of a spring, the spring affixed to the base structure and extending into the recess, the placing including placing the magnet on a side of the electromagnetic actuator, between the spring and the side of the electromagnetic actuator, the spring pressing the magnet against the side of the electromagnetic actuator and maintaining a position of the magnet in response to the placing the magnet within the recess.Type: GrantFiled: November 17, 2016Date of Patent: November 13, 2018Assignee: Intel CorporationInventors: Robert Starkston, Amanuel M. Abebaw, Liwei Wang, Mark Saltas, Sandeep S. Iyer, Nick Labanok
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Publication number: 20180226334Abstract: Embodiments herein may relate to a package that includes a package substrate with a first die on a first side of the package substrate and a second die on a second side of the package substrate. Solder balls may be coupled with the second side of the package substrate and the second die such that the solder balls are approximately coplanar.Type: ApplicationFiled: August 27, 2015Publication date: August 9, 2018Inventors: ROBERT L. SANKMAN, ALLAN A. OVROM, III, ROBERT STARKSTON, OREN ARAD
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Patent number: 10008452Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.Type: GrantFiled: March 27, 2017Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Qing Ma, Johanna M. Swan, Robert Starkston, John S. Guzek, Robert L. Sankman, Aleksandar Aleksov
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Publication number: 20180134547Abstract: Apparatuses, systems, and methods associated with placement of magnets within a microelectromechanical system device are disclosed herein. In embodiments, a method of affixing at least one magnet in a microelectromechanical system, may include affixing an electromagnetic actuator to a base structure of the microelectromechanical system, the affixing including affixing the electromagnetic actuator within a recess formed in the base structure. The method may further include placing a magnet within the recess, wherein the recess includes at least a portion of a spring, the spring affixed to the base structure and extending into the recess, the placing including placing the magnet on a side of the electromagnetic actuator, between the spring and the side of the electromagnetic actuator, the spring pressing the magnet against the side of the electromagnetic actuator and maintaining a position of the magnet in response to the placing the magnet within the recess.Type: ApplicationFiled: November 17, 2016Publication date: May 17, 2018Inventors: Robert Starkston, Amanuel M. Abebaw, Liwei Wang, Mark Saltas, Sandeep S. Iyer, Nick Labanok
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Patent number: 9832860Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.Type: GrantFiled: September 26, 2014Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Robert Starkston, John Guzek, Patrick Nardi, Keith Jones, Javier Soto Gonzalez
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Publication number: 20170287831Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: June 12, 2017Publication date: October 5, 2017Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
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Publication number: 20170200677Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Applicant: INTEL CORPORATIONInventors: Qing Ma, Johanna M. Swan, Robert Starkston, John S. Guzek, Robert L. Sankman, Aleksandar Aleksov
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Patent number: 9679843Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: February 22, 2016Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
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Patent number: 9642248Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.Type: GrantFiled: February 10, 2015Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Qing Ma, Johanna M. Swan, Robert Starkston, John S. Guzek, Robert L. Sankman, Aleksandar Aleksov
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Publication number: 20160268213Abstract: An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.Type: ApplicationFiled: March 9, 2015Publication date: September 15, 2016Inventors: Hongjin JIANG, Robert STARKSTON, Digvijay A. RAORANE, Keith D. JONES, Ashish DHALL, Omkar G. KARHADE, Kedar DHANE, Suriyakala RAMALINGAM, Li-Sheng WENG, Robert F. CHENEY, Patrick N. STOVER
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Publication number: 20160197037Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: February 22, 2016Publication date: July 7, 2016Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
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Publication number: 20160095209Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Robert STARKSTON, John GUZEK, Patrick NARDI, Keith JONES, Javier SOTO GONZALEZ
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Patent number: 9269701Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: August 5, 2015Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20150340353Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: August 5, 2015Publication date: November 26, 2015Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Patent number: 9136236Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: September 28, 2012Date of Patent: September 15, 2015Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20150156869Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.Type: ApplicationFiled: February 10, 2015Publication date: June 4, 2015Applicant: INTEL CORPORATIONInventors: Qing Ma, Johanna M. Swan, Robert Starkston, John S. Guzek, Robert L. Sankman, Aleksandar Aleksov
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Patent number: 9001520Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.Type: GrantFiled: September 24, 2012Date of Patent: April 7, 2015Assignee: Intel CorporationInventors: Qing Ma, Johanna M. Swan, Robert Starkston, John S. Guzek, Robert L. Sankman, Aleksandar Aleksov
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Publication number: 20140091474Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan