Patents by Inventor Robert Starkston

Robert Starkston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140085846
    Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Inventors: Qing Ma, Johanna M. Swan, Robert Starkston, John S. Guzek, Robert L. Sankman, Aleksandar Aleksov
  • Patent number: 8364304
    Abstract: A method for singulating dies from a wafer includes laser scribing a continuous line on each side of the die, and laser ablating an area adjacent the laser scribed continuous line on each side of the die. The laser ablations in the area adjacent the laser scribed continuous line on each side of the die being spaced from one another. The method also includes sawing the laser abated area adjacent the continuous line. A method for singulating dies from a wafer includes laser scribing a first continuous line, laser scribing a second continuous line spaced apart from the first continuous line, and laser scribing a third continuous line. The third continuous line positioned between the first continuous line and the second continuous line. The third continuous line overlaps the second continuous line and the third continuous line.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Andrew Proctor, Steve Terry
  • Publication number: 20100279490
    Abstract: A method for singulating dies from a wafer includes laser scribing a continuous line on each side of the die, and laser ablating an area adjacent the laser scribed continuous line on each side of the die. The laser ablations in the area adjacent the laser scribed continuous line on each side of the die being spaced from one another. The method also includes sawing the laser abated area adjacent the continuous line. A method for singulating dies from a wafer includes laser scribing a first continuous line, laser scribing a second continuous line spaced apart from the first continuous line, and laser scribing a third continuous line. The third continuous line positioned between the first continuous line and the second continuous line. The third continuous line overlaps the second continuous line and the third continuous line.
    Type: Application
    Filed: July 14, 2010
    Publication date: November 4, 2010
    Inventors: Robert Starkston, Andrew Proctor, Steve Terry
  • Patent number: 7772090
    Abstract: A method for singulating dies from a wafer includes laser scribing a continuous line on each side of the die, and laser ablating an area adjacent the laser scribed continuous line on each side of the die. The laser ablations in the area adjacent the laser scribed continuous line on each side of the die being spaced from one another. The method also includes sawing the laser abated area adjacent the continuous line. A method for singulating dies from a wafer includes laser scribing a first continuous line, laser scribing a second continuous line spaced apart from the first continuous line, and laser scribing a third continuous line. The third continuous line positioned between the first continuous line and the second continuous line. The third continuous line overlaps the second continuous line and the third continuous line.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 10, 2010
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Andrew Proctor, Steve Terry
  • Patent number: 7332423
    Abstract: One example electronic assembly includes a substrate that has a plurality of contacts which become bonded to a plurality of contacts on a die. The electronic assembly further includes a male member that extends from at least one of the substrate and the die and a female member that extends from the other of the substrate and the die. The male member is inserted into the female member to align the die relative to the substrate. The male member and the female member may have any configuration as long as one or more portions of the male member extend partially, or wholly, into the female member. An example method includes aligning a die relative to a substrate by inserting a male member that extends from one of the die and the substrate into a female member that extends from the other of the die and the substrate.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Sridhar Narasimhan, Chia-Pin Chiu, Suzana Prstic, Patrick N Stover, Hong Xie
  • Patent number: 7223638
    Abstract: A thermally conductive member is placed adjacent a microelectronic die with a thermal interface material between the microelectronic die and a wetting layer formed on a surface of the thermally conductive member. The thermal interface material is heated to cause reflow thereof. The first portion of the thermal interface material is directed by the wetting layer into a first cavity formed in the thermally conductive member. The thermal interface material is then allowed to cool and solidify.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventor: Robert Starkston
  • Publication number: 20070001318
    Abstract: One example electronic assembly includes a substrate that has a plurality of contacts which become bonded to a plurality of contacts on a die. The electronic assembly further includes a male member that extends from at least one of the substrate and the die and a female member that extends from the other of the substrate and the die. The male member is inserted into the female member to align the die relative to the substrate. The male member and the female member may have any configuration as long as one or more portions of the male member extend partially, or wholly, into the female member. An example method includes aligning a die relative to a substrate by inserting a male member that extends from one of the die and the substrate into a female member that extends from the other of the die and the substrate.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Robert Starkston, Sridhar Narasimhan, Chia-Pin Chiu, Suzana Prstic, Patrick Stover, Hong Xie
  • Patent number: 7015592
    Abstract: A marking is formed on an underfill between a die and a substrate.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: March 21, 2006
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Jason Zhang
  • Publication number: 20050255635
    Abstract: A thermally conductive member is placed adjacent a microelectronic die with a thermal interface material between the microelectronic die and a wetting layer formed on a surface of the thermally conductive member. The thermal interface material is heated to cause reflow thereof. The first portion of the thermal interface material is directed by the wetting layer into a first cavity formed in the thermally conductive member. The thermal interface material is then allowed to cool and solidify.
    Type: Application
    Filed: May 13, 2004
    Publication date: November 17, 2005
    Inventor: Robert Starkston
  • Publication number: 20050206017
    Abstract: A marking is formed on an underfill between a die and a substrate.
    Type: Application
    Filed: March 19, 2004
    Publication date: September 22, 2005
    Inventors: Robert Starkston, Jason Zhang
  • Publication number: 20050067391
    Abstract: A method for singulating dies from a wafer includes laser scribing a continuous line on each side of the die, and laser ablating an area adjacent the laser scribed continuous line on each side of the die. The laser ablations in the area adjacent the laser scribed continuous line on each side of the die being spaced from one another. The method also includes sawing the laser abated area adjacent the continuous line. A method for singulating dies from a wafer includes laser scribing a first continuous line, laser scribing a second continuous line spaced apart from the first continuous line, and laser scribing a third continuous line. The third continuous line positioned between the first continuous line and the second continuous line. The third continuous line overlaps the second continuous line and the third continuous line.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Robert Starkston, Andrew Proctor, Steve Terry
  • Patent number: 6617683
    Abstract: A microprocessor package and a method of dissipating heat therefrom have improved thermal performance by utilizing low modulus thermal interface material between the flip chip, central processing unit and a heat spreader in the package. A modulus of elasticity of the thermal interface material in the kPa range is preferably provided by a cured, filled polymer gel which is lightly crosslinked. The gel thermal interface material enables the package to have a post end-of-line and post reliability testing thermal resistance across the thermal interface material between the flip chip and the heat spreader of <0.45 cm2° C./Watt. Mitigation of thin film cracking in die and prevention of interfacial delamination upon temperature cycling are also attained.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: September 9, 2003
    Assignee: Intel Corporation
    Inventors: Vassoudevane Lebonheur, Robert Starkston
  • Publication number: 20030067069
    Abstract: A microprocessor package and a method of dissipating heat therefrom have improved thermal performance by utilizing low modulus thermal interface material between the flip chip, central processing unit and a heat spreader in the package. A modulus of elasticity of the thermal interface material in the kPa range is preferably provided by a cured, filled polymer gel which is lightly crosslinked. The gel thermal interface material enables the package to have a post end-of-line and post reliability testing thermal resistance across the thermal interface material between the flip chip and the heat spreader of <0.45 cm2 ° C./Watt. Mitigation of thin film cracking in die and prevention of interfacial delamination upon temperature cycling are also attained.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 10, 2003
    Inventors: Vassoudevane Lebonheur, Robert Starkston
  • Patent number: 6239973
    Abstract: An electronic cartridge which includes a cover that is electrically coupled to a substrate by a clip. An integrated circuit package is mounted to the substrate and at least partially enclosed by the cover. The clips and cover may be connected to a ground plane of the substrate. The cover and substrate may create a “shield” about the integrated circuit package so that any electromagnetic field that flows from the package is grounded to the substrate.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: May 29, 2001
    Assignee: Intel Corporation
    Inventors: Scot W. Taylor, Robert Starkston, Charles Gealer, Michael L. Rutigliano, Raymond A. Krick, John A. Rabenius, Edmond L. Hart, Ravi V. Mahajan, Farukh Fares
  • Patent number: 6191475
    Abstract: A substrate for reducing electromagnetic emissions is provided. The substrate may include a plurality of ground layers, signal layers and power layers. All of the layers other than the ground layer are provided with a ground ring that may extend around the perimeter of the layer. The ground rings are electrically coupled together by ground stitching or vias that are randomly spaced. The random spacing of the ground stitching is based on the operating frequencies of the integrated circuit devices mounted on the substrate. Additional shielding may be provided by providing a cover assembly made of any conductive material that is coupled to the exposed ground rings on the uppermost and lowermost surfaces of the substrate. The cover assembly is coupled to the exposed ground rings in a randomized pattern. The device provides a virtual electrical ground cage in which the internal signal layers are totally enclosed, thereby reducing electromagnetic emissions.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Harry G. Skinner, Neil C. Delaplane, Ravi V. Mahajan, Robert Starkston, Mirng-ji Lii, Ron Edsall
  • Patent number: 6043560
    Abstract: A method and apparatus for controlling the thickness of a thermal interface between a processor die and a thermal plate in a microprocessor assembly are provided. The apparatus includes a generally rectangular shaped thermal top cover having a recessed portion of predetermined depth and aperture therein. The thermal top cover fits over the processor die. A thermal interface layer fills the recessed portion of the thermal top cover covering the processor die. The depth of the recessed portion is greater than the thickness of the processor die so that the thickness of the thermal interface layer is controlled. A thermal plate is placed over the thermal top cover in contact with the thermal grease so as to form a thermal path from the processor die to the thermal plate.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: March 28, 2000
    Assignee: Intel Corporation
    Inventors: Kevin J. Haley, Niel C. Delaplane, Ravindranath V. Mahajan, Robert Starkston, Charles A. Gealer, Joseph C. Krauskopf
  • Patent number: 6043983
    Abstract: An electronic cartridge which includes a cover that is electrically coupled to a substrate by a clip. An integrated circuit package is mounted to the substrate and at least partially enclosed by the cover. The clips and cover may be connected to a ground plane of the substrate. The cover and substrate may create a "shield" about the integrated circuit package so that any electro-magnetic field that flows from the package is grounded to the substrate.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: March 28, 2000
    Assignee: Intel Corporation
    Inventors: Scot W. Taylor, Robert Starkston, Charles Gealer, Michael L. Rutigliano, Raymond A. Krick, John A. Rabenius, Edmond L. Hart, Ravi V. Mahajan, Farukh Fares
  • Patent number: 4647397
    Abstract: Process and composition for removing H.sub.2 S and like sulfides from gas streams by contact with a substituted aromatic nitrile having an electron-attracting substituent on the aromatic ring at least as strong as halogen (e.g., isophthalonitrile) and an organic tertiary amine in an inert organic solvent such as N-methyl-2-pyrrolidone.
    Type: Grant
    Filed: April 29, 1985
    Date of Patent: March 3, 1987
    Assignee: Chevron Research Company
    Inventors: Robert Starkston, Mark C. Luce, Robert V. Homsy
  • Patent number: 4539189
    Abstract: Process and composition for removing H.sub.2 S and like sulfides from gas streams by contact with a substituted aromatic nitrile having an electron-attracting substituent on the aromatic ring at least as strong as halogen (e.g., isophthalonitrile) and an organic tertiary amine in an inert organic solvent such as N-methyl-2-pyrrolidone.
    Type: Grant
    Filed: January 23, 1984
    Date of Patent: September 3, 1985
    Assignee: Chevron Research Company
    Inventors: Robert Starkston, Mark C. Luce, Robert V. Homsy