Patents by Inventor Robert Strittmatter

Robert Strittmatter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240413205
    Abstract: A gallium nitride (GaN) transistor which includes a multi-layer/multi-thickness barrier layer formed of segments of progressively increasing thickness between the gate and drain to progressively increase the 2DEG density in the channel from gate to drain. The GaN gate can be formed on the base barrier layer to produce an enhancement mode device with a positive threshold voltage. By forming the gate over a thicker segment of the barrier layer, a GaN transistor with a less positive threshold voltage, or a depletion mode transistor with a negative threshold voltage, can be produced.
    Type: Application
    Filed: June 6, 2024
    Publication date: December 12, 2024
    Applicant: Efficient Power Conversion Corporation
    Inventors: Robert Beach, Christopher Rutherglen, Robert Strittmatter, Jianjun Cao, Alexander Lidow
  • Publication number: 20240274681
    Abstract: An enhancement mode gallium nitride (GaN) transistor with a p-type gate configured to eliminate holes accumulating under the gate metal. The gate has two electrodes, a gate electrode and a hole collector electrode. In a preferred embodiment, a negative voltage is applied to the hole collector electrode, attracting holes accumulating under the gate metal. The attracted holes recombine with electrons supplied by the negative voltage, thereby substantially eliminating the holes.
    Type: Application
    Filed: February 8, 2024
    Publication date: August 15, 2024
    Applicant: Efficient Power Conversion Corporation
    Inventors: Robert Strittmatter, Jianjun Cao, Robert Beach, Muskan Sharma, Wen-Chia Liao, Alexander Lidow, Massimo Grasso, Sergio Morini
  • Publication number: 20240234521
    Abstract: An enhancement mode GaN transistor that includes a multi-region field plate which partially overlaps the gate and partially overlaps a barrier offset layer. The multi-region field plate includes a section of increased height with respect to the channel layer over the portion of the gate nearest the drain contact, and a section of reduced height with respect to the channel layer over the edge or transition of the barrier offset layer, minimizing the peak electric field at the corner of the gate and at the edge or transition of the barrier offset layer.
    Type: Application
    Filed: January 9, 2024
    Publication date: July 11, 2024
    Applicant: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Wen-Chia Liao, Muskan Sharma, Robert Strittmatter, Alexander Lidow
  • Patent number: 10312260
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: June 4, 2019
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. de Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Patent number: 10096702
    Abstract: A gallium nitride (GaN) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the gate and drain (near the gate) minimizes the gate leakage and fields near the gate that cause high gate-drain charge (Qgd). A second insulator (or multiple insulators), disposed between the first insulator and the drain, minimizes electric fields at the drain contact and provides a high density of charge in the channel for low on-resistance.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 9, 2018
    Assignee: Efficient Power Conversion Corporation
    Inventors: Robert Beach, Robert Strittmatter, Chunhua Zhou, Guangyuan Zhao, Jianjun Cao
  • Patent number: 10090274
    Abstract: A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: October 2, 2018
    Assignee: Efficient Power Conversion Corporation
    Inventors: Robert Strittmatter, Seshadri Kolluri, Robert Beach, Jianjun Cao, Alana Nakata
  • Publication number: 20170352754
    Abstract: A gallium nitride (GaN) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the gate and drain (near the gate) minimizes the gate leakage and fields near the gate that cause high gate-drain charge (Qgd). A second insulator (or multiple insulators), disposed between the first insulator and the drain, minimizes electric fields at the drain contact and provides a high density of charge in the channel for low on-resistance.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 7, 2017
    Inventors: Robert Beach, Robert Strittmatter, Chunhua Zhou, Guangyuan Zhao, Jianjun Cao
  • Patent number: 9837438
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: December 5, 2017
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20170330898
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Application
    Filed: July 20, 2017
    Publication date: November 16, 2017
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. de Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Patent number: 9583480
    Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 28, 2017
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Patent number: 9331191
    Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 3, 2016
    Assignee: Efficient Power Conversion Corporation
    Inventors: Stephen L. Colino, Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20160111416
    Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
    Type: Application
    Filed: December 3, 2015
    Publication date: April 21, 2016
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20160086980
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 24, 2016
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Patent number: 9214461
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: December 15, 2015
    Assignee: Efficient Power Coversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Patent number: 9214399
    Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 15, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Patent number: 9214528
    Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: December 15, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao
  • Patent number: 9171911
    Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 27, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao
  • Publication number: 20150270241
    Abstract: A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.
    Type: Application
    Filed: March 24, 2015
    Publication date: September 24, 2015
    Inventors: ROBERT STRITTMATTER, Seshadri Kolluri, Robert Beach, Jianjun Cao, Alana Nakata
  • Publication number: 20150034962
    Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20150028384
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 29, 2015
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar