Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space may have entries that include data values associated with the address space identifier.

Abstract: In one embodiment of the present invention, a method includes invalidating an entry of a filter coupled to a pipeline resource if an update to the entry occurs during a first context; and flushing a portion of the pipeline resource corresponding to an address space including the entry.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: A computer chipset having an identifier module and a router. The identifier module is configured to add sequence identifiers to each transaction in independent ordered sequences of transactions. The sequence identifiers identify which ordered sequence the transactions belong to. The identifier module combines the ordered sequences of transactions into a combined ordered sequence of transactions. The combined ordered sequence of transactions are sent over an ordered interface. A router then separates the combined ordered sequence of transactions into ordered queues based on the sequence identifiers associated with the transactions. The transactions in the ordered queues are executed in an order that reduces the time required to complete the transactions.

Abstract: A method of invalidating a cache line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another node without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: A system and method for permitting the execution of system management mode (SMM) code during secure operations in a microprocessor system is described. In one embodiment, the system management interrupt (SMI) may be first directed to a handler in a secured virtual machine monitor (SVMM). The SMI may then be re-directed to SMM code located in a virtual machine (VM) that is under the security control of the SVMM. This redirection may be accomplished by allowing the SVMM to read and write the system management (SM) base register in the processor.

Abstract: A computer chipset having an identifier module and a router. The identifier module is configured to add sequence identifiers to each transaction in independent ordered sequences of transactions. The sequence identifiers identify which ordered sequence the transactions belong to. The identifier module combines the ordered sequences of transactions into a combined ordered sequence of transactions. The combined ordered sequence of transactions are sent over an ordered interface. A router then separates the combined ordered sequence of transactions into ordered queues based on the sequence identifiers associated with the transactions. The transactions in the ordered queues are executed in an order that reduces the time required to complete the transactions.

Abstract: An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value in order to establish security verification of secure software within the secure memory environment.

Abstract: A system and method utilizing distributed caches. More particularly, the present invention pertains to a scalable method of improving the bandwidth and latency performance of caches through the implementation of distributed caches. Distributed caches remove the detrimental architectural and implementation impacts of single monolithic cache systems.

Abstract: A method of invalidating cache a line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another nodes without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.