Patents by Inventor Robert Tsu
Robert Tsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7402514Abstract: An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.Type: GrantFiled: January 24, 2003Date of Patent: July 22, 2008Assignee: Texas Instruments IncorporatedInventors: Robert Tsu, Joe W. McPherson, William R. McKee, Thomas Bonifield
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Patent number: 6951812Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.Type: GrantFiled: December 17, 2003Date of Patent: October 4, 2005Assignee: Texas Instruments IncorporatedInventors: Qing-Tang Jiang, Robert Tsu, Kenneth D. Brennan
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Publication number: 20040147112Abstract: An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.Type: ApplicationFiled: January 24, 2003Publication date: July 29, 2004Inventors: Robert Tsu, Joe W. McPherson, William R. McKee, Thomas Bonifield
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Publication number: 20040132282Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.Type: ApplicationFiled: December 17, 2003Publication date: July 8, 2004Inventors: Qing-Tang Jiang, Robert Tsu, Kenneth D. Brennan
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Patent number: 6696337Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.Type: GrantFiled: June 11, 2002Date of Patent: February 24, 2004Assignees: Hitachi, Ltd., Texas Instruments Inc.Inventors: Isamu Asano, Robert Tsu
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Patent number: 6693356Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.Type: GrantFiled: March 27, 2002Date of Patent: February 17, 2004Assignee: Texas Instruments IncorporatedInventors: Qing-Tang Jiang, Robert Tsu, Kenneth D. Brennan
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Patent number: 6653676Abstract: The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.Type: GrantFiled: July 30, 2001Date of Patent: November 25, 2003Assignee: Texas Instruments IncorporatedInventors: Robert Tsu, Isamu Asano, Shinpei Iijima, William R. McKee
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Publication number: 20030186543Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.Type: ApplicationFiled: March 27, 2002Publication date: October 2, 2003Inventors: Qing-Tang Jiang, Robert Tsu, Kenneth D. Brennan
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Publication number: 20020155662Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.Type: ApplicationFiled: June 11, 2002Publication date: October 24, 2002Inventors: Isamu Asano, Robert Tsu
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Patent number: 6461955Abstract: A dual damascene process. After the via etch, a via protect layer (114) is deposited in the via (112). The via protect layer (114) comprises a material that has a dry etch rate at least equal to that of the IMD (108) and a wet etch rate that is approximately 100 times that of the IMD (108) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern (120) is formed and both the via protect layer (114) and IMD (108) are etched. The remaining portions of the via protect layer (114) are then removed prior to forming the metal layer (122).Type: GrantFiled: March 9, 2000Date of Patent: October 8, 2002Assignee: Texas Instruments IncorporatedInventors: Robert Tsu, Qi-Zhong Hong, William R. Mckee
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Patent number: 6417045Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.Type: GrantFiled: August 22, 2000Date of Patent: July 9, 2002Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Isamu Asano, Robert Tsu
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Publication number: 20020043681Abstract: An embodiment of the instant invention is a semiconductor device having at least two memory cells fabricated over a semiconductor substrate, the semiconductor device comprising: a first memory cell comprised of a bottom electrode having a bottom portion (230) and a vertical portion (232) and a capacitor dielectric (219); a second memory cell comprised of a bottom electrode having a bottom portion (230) and a vertical portion (232) and the capacitor dielectric (219); a pillar of insulating material (214) situated between the vertical portion of the first memory device and the vertical portion of the second memory cell; and wherein the capacitor dielectric extends along the vertical portion and the bottom portion of the first memory cell, the vertical portion and the bottom portion of the second memory cell, and on top of the pillar of insulating material. Preferably, the pillar of insulating material is comprised of: silicon dioxide, BPSG, PSG, PETEOS, TEOS, xerogel, aerogel, HSQ, or a combination thereof.Type: ApplicationFiled: April 10, 2001Publication date: April 18, 2002Inventors: Robert Tsu, Ming Yang
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Publication number: 20020014646Abstract: The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.Type: ApplicationFiled: July 30, 2001Publication date: February 7, 2002Inventors: Robert Tsu, Isamu Asano, Shinpei Iijima, William R. McKee
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Patent number: 6331325Abstract: A semiconductor device and process for making the same are disclosed which incorporate boron, which has been found to be substantially insoluble in BST, into a BST dielectric film 24. Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Boron included in a BST precursor may be used to form boron oxide in a second phase 30, which is distributed in boundary regions between BST crystals 28 in film 24. It is believed that the inclusion of boron allows for BST grains of a desired size to be formed at lower temperature, and also reduces the leakage current of the capacitive structure.Type: GrantFiled: September 30, 1994Date of Patent: December 18, 2001Assignee: Texas Instruments IncorporatedInventors: Bernard M. Kulwicki, Robert Tsu
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Patent number: 6294420Abstract: The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.Type: GrantFiled: January 28, 1998Date of Patent: September 25, 2001Assignee: Texas Instruments IncorporatedInventors: Robert Tsu, Isamu Asano, Shinpei Iijima, William R. McKee
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Patent number: 6207561Abstract: A cost-effective method for fabricating MIM capacitors (120). After metal (106) deposition, the metal oxide (108) is formed using an oxidation chemistry that includes CO2 and H2. The CO2/H2 gas ratio is controlled for selective oxidation. Thus, the metal (106) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagent.Type: GrantFiled: July 29, 1999Date of Patent: March 27, 2001Assignee: Texas Instruments IncorporatedInventors: Ming Hwang, Robert Tsu, Wei-Yung Hsu
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Patent number: 6168985Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.Type: GrantFiled: June 15, 1999Date of Patent: January 2, 2001Assignees: Hitachi, Ltd., Texas Instruments Inc.Inventors: Isamu Asano, Robert Tsu
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Patent number: 6096597Abstract: In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O.sub.2 plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be useful in forming a capacitor 12 dielectric 24. In turn, the capacitor could be used in a DRAM memory device.Type: GrantFiled: January 28, 1998Date of Patent: August 1, 2000Assignee: Texas Instruments IncorporatedInventors: Robert Tsu, William R. McKee, Shimpei Iijima, Isamu Asano, Masato Kunitomo, Tsuyoshi Tamaru
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Patent number: 6060354Abstract: A method for forming a semiconductor memory device storage cell structure having an increased surface area. The storage cell structure has one or more rough polysilicon surfaces formed by depositing the polysilicon under conditions that result in gas phase dominant nucleation.Type: GrantFiled: December 18, 1997Date of Patent: May 9, 2000Assignee: Texas Instruments IncorporatedInventors: Robert Tsu, William R. McKee, Ming-Jang Hwang
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Patent number: 6037207Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.Type: GrantFiled: November 13, 1997Date of Patent: March 14, 2000Assignees: Hitachi, Ltd., Texas Instruments, Inc.Inventors: Isamu Asano, Robert Tsu