Patents by Inventor Robert Tsu

Robert Tsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5731220
    Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of erbium dopant (1 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size. including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without erbium precipitation than are observed for bulk BST. For erbium doping levels generally between 1% and 3%, over an order of magnitude decrease in leakage current (compared to undoped BST) may be achieved for such films.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 24, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Tsu, Bernard M. Kulwicki
  • Patent number: 5635741
    Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of erbium dopant (1 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size, including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without erbium precipitation than are observed for bulk BST. For erbium doping levels generally between 1% and 3%, over an order of magnitude decrease in leakage current (compared to undoped BST) may be achieved for such films.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: June 3, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Tsu, Bernard M. Kulwicki
  • Patent number: 5617290
    Abstract: A semiconductor device and process for making the same are disclosed which incorporate boron, which has been found to be substantially insoluble in BST, into a BST dielectric film 24. Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Boron included in a BST precursor may be used to form boron oxide in a second phase 30, which is distributed in boundary regions between BST crystals 28 in film 24. It is believed that the inclusion of boron allows for BST grains of a desired size to be formed at lower temperature, and also reduces the leakage current of the capacitive structure.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 1, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Bernard M. Kulwicki, Robert Tsu
  • Patent number: 5609927
    Abstract: Processing techniques for processing high-dielectric-constant material are provided to allow for the formation of an electronic device (10) which comprises a inner electrode (24), a high-dielectric-constant layer (28), and an outer electrode (30). High-dielectric-constant layer (28) is subjected to ultraviolet radiation in an oxygen ozone ambient to eliminate various undesirable hydroxide and carbonate compounds. Layer (28) is further subjected to high pressure isotropic reactive ion etches prior to the deposition of layer (30). The interface between layer (28) and layer (30) is exposed to reactive fluorine and low pressure plasma to improve the fair electric properties and leakage currents associated with layer (28).
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 11, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Howard R. Beratan, Robert Tsu
  • Patent number: 5453908
    Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of holmium dopant (0.5 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size, including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without holmium precipitation than are observed for bulk BST. For holmium doping levels generally between 0.5 and 5% (compensated with titanium and/or manganese), better than 50% improvement in dielectric constant and two to six orders of magnitude reduction in leakage current (compared to undoped BST) have been observed for such films.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: September 26, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Tsu, Bernard M. Kulwicki
  • Patent number: 5432128
    Abstract: This invention encompasses using a strengthened shell to enhance reliability of aluminum leads of a semiconductor device. The invention includes depositing an aluminum layer on a substrate 12, etching the aluminum layer in a predetermined pattern to form aluminum leads 16, exposing the aluminum leads 16 to a strengthening gas to react and form a strengthened shell 18 on the aluminum leads 16, and depositing a dielectric layer 20 over the strengthened shell 18 and the substrate 12. The strengthening gas may contain nitrogen, oxygen, or both. The exposing step may also comprise a rapid thermal anneal, and the dielectric layer 20 is preferably comprised of a material having a dielectric constant of less than 3. An advantage of the invention is to mechanically strengthen the aluminum leads of a semiconductor wafer. In addition, it is an intrinsic operation, rather than extrinsic; the basic material required is already present on the wafer, it is merely altered.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: July 11, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Robert Tsu