Patents by Inventor Robert Van Veldhoven

Robert Van Veldhoven has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030934
    Abstract: A continuous-time delta-sigma modulator, CTDSM (400, 500, 700, 800) is described that comprises: an operational transconductance amplifier, OTA, (406, 506, 706, 806) having an input port (404, 504, 719, 739, 819, 839) configured to receive an analog input signal and an output port (408, 508, 707, 708, 807, 808); an input low pass filter network comprising at least one input resistor, R1, (402, 502, 702, 722, 802, 822) at least one first shunt capacitor, C1, (403, 503, 703, 803) and at least one feedback resistor, Rdac (410, 510, 710, 810, 730, 830) connected to the input port of the OTA; an output filter network comprising a shunt second resistor, R2, (415, 515, 715, 815) in parallel to a second shunt capacitor, C2, (414, 514, 714, 814), and coupled to the output port (408, 508, 707, 708, 807, 808) of the OTA; a quantizer (413, 513, 713, 813) connected to the output filter network and having at least one output connected to the input port of the OTA via the at least one feedback resistor, Rdac; and wherein th
    Type: Application
    Filed: November 3, 2022
    Publication date: January 25, 2024
    Inventors: Victor Pecanins Martinez, Robert van Veldhoven
  • Publication number: 20230421172
    Abstract: An interface circuit includes an analogue to digital converter having an input configured to receive an input signal having an unknown DC bias voltage via an input resistance and provide an output signal to an ADC feedback loop. The ADC feedback loop includes a digital filter arranged to digitally filter the fedback output signal. A digital to analogue converter (DAC) forming a DC feedback loop with the ADC and arranged to convert the digitally filtered fedback output signal to an analogue signal that is provided to the input of the ADC, wherein the analogue signal that is provided to the input of the ADC is arranged to include a DC bias component that is comparable to a DC bias component of a current of the input signal passing through the input resistor.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 28, 2023
    Inventor: Robert van Veldhoven
  • Patent number: 11722146
    Abstract: Systems and methods for correction of sigma-delta analog-to-digital converters (ADCs) using neural networks are described. In an illustrative, non-limiting embodiment, a device may include: an ADC; a filter coupled to the ADC, where the filter is configured to receive an output from the ADC and to produce a filtered output; and a neural network coupled to the filter, where the neural network is configured to receive the filtered output and to produce a corrected output.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: August 8, 2023
    Assignee: NXP B.V.
    Inventor: Robert van Veldhoven
  • Publication number: 20230238981
    Abstract: Systems and methods for correction of sigma-delta analog-to-digital converters (ADCs) using neural networks are described. In an illustrative, non-limiting embodiment, a device may include: an ADC; a filter coupled to the ADC, where the filter is configured to receive an output from the ADC and to produce a filtered output; and a neural network coupled to the filter, where the neural network is configured to receive the filtered output and to produce a corrected output.
    Type: Application
    Filed: January 21, 2022
    Publication date: July 27, 2023
    Applicant: NXP B.V.
    Inventor: Robert van Veldhoven
  • Patent number: 11695377
    Abstract: An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: July 4, 2023
    Assignee: NXP B.V.
    Inventors: Robert van Veldhoven, John Pigott
  • Patent number: 11658620
    Abstract: A digital signal generator apparatus and method is described. The digital signal generator includes a counter, an integrator and a comparator. The counter counts up or down from an initial counter value dependent on a counter control input. The comparator has a first input coupled to the counter output, a threshold input and a comparator output coupled to the counter control input. The integrator has an input coupled to the counter output and an output coupled to the digital signal generator output. The digital signal generator determines the count direction after the initial direction dependent on the comparison between a threshold value applied to the threshold input and the counter output value. The digital signal generator may implement the generation of a waveform having an approximation to a raised cosine function. The generated waveform may be used for audio artefact reduction in an audio amplifier during mute or unmute operations or during power up power down operations.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 23, 2023
    Assignee: NXP B.V.
    Inventors: Robert van Veldhoven, Khalid Mabtoul, Dmitrij Andreevits Sjwed
  • Publication number: 20230118374
    Abstract: An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Inventors: Robert van Veldhoven, John Pigott
  • Publication number: 20230038361
    Abstract: A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 9, 2023
    Inventor: Robert van Veldhoven
  • Patent number: 11502698
    Abstract: A passive sigma-delta modulator including first modulator loop, a second modulator loop, and a digital combiner providing an output signal. The first modulator loop includes a first quantizer, a first passive summing junction, a first continuous-time passive analog loop filter, and a first feedback path. The second modulator loop includes a second quantizer, analog transfer circuitry, a second continuous-time passive summing junction, a second passive analog loop filter, a second feedback path, and digital transfer circuitry having a gain that is substantially a reciprocal of the analog transfer circuitry. A digital noise cancelation filter may be located between the first quantizer and the digital combiner, or an analog noise cancelation filter may be provided within the second modulator loop. Single-ended or differential configurations are contemplated.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: November 15, 2022
    Assignee: NXP B.V.
    Inventor: Robert van Veldhoven
  • Publication number: 20220236119
    Abstract: An integrated circuit (IC) chip includes a first temperature sensor of a first type and a second temperature sensor of a second type that differs from the first type. A method implemented in the IC chip entails calibrating the second temperature sensor utilizing the first temperature sensor and following the calibrating operation, sensing a temperature of the IC chip utilizing the second temperature sensor. The first temperature sensor may be a bipolar junction transistor-based temperature sensor configured to undergo a voltage calibration. Alternatively, the first temperature sensor may be a thermal-diffusivity-based temperature sensor. The second temperature sensor may be a low power consumption sensor relative to the first temperature sensor, and the first temperature sensor may be powered off following calibration of the second temperature sensor.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Robert van Veldhoven, Sha Xia
  • Publication number: 20220123696
    Abstract: A digital signal generator apparatus and method is described. The digital signal generator includes a counter, an integrator and a comparator. The counter counts up or down from an initial counter value dependent on a counter control input. The comparator has a first input coupled to the counter output, a threshold input and a comparator output coupled to the counter control input. The integrator has an input coupled to the counter output and an output coupled to the digital signal generator output. The digital signal generator determines the count direction after the initial direction dependent on the comparison between a threshold value applied to the threshold input and the counter output value. The digital signal generator may implement the generation of a waveform having an approximation to a raised cosine function. The generated waveform may be used for audio artefact reduction in an audio amplifier during mute or unmute operations or during power up power down operations.
    Type: Application
    Filed: August 27, 2021
    Publication date: April 21, 2022
    Inventors: Robert van Veldhoven, Khalid Mabtoul, Dmitrij Andreevits Sjwed
  • Publication number: 20220019883
    Abstract: Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which may utilize a reference ADC or a digital training signal representing a reference ADC that has less distortion errors than the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 20, 2022
    Applicant: NXP B.V.
    Inventor: Robert van Veldhoven
  • Patent number: 11101810
    Abstract: Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which utilizes a filtered output of the analog-to-digital converter that has less distortion errors than the unfiltered output of the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 24, 2021
    Assignee: NXP B.V.
    Inventor: Robert van Veldhoven
  • Publication number: 20190158108
    Abstract: The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.
    Type: Application
    Filed: September 5, 2018
    Publication date: May 23, 2019
    Inventors: Robert Van Veldhoven, Alphons Litjes, Erik Olieman
  • Patent number: 10284220
    Abstract: The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 7, 2019
    Assignee: NXP B.V.
    Inventors: Robert Van Veldhoven, Alphons Litjes, Erik Olieman
  • Patent number: 10014873
    Abstract: A digital-to-analog converter (DAC) includes a plurality of resistive elements connected together in series to form a ring of resistive elements. A node is formed by each of the connections of adjacent resistive elements of the ring. Groups of parallel-connected switches are coupled to each node. A first switch of the group of switches is for selectively coupling a first power supply voltage terminal to the node. A second switch of the group of switches is for selectively coupling a second power supply voltage to the node. A third switch of the group of switches is for selectively coupling an output terminal to the node. A differential or single-ended analog output may be provided. Mismatch induced error is removed using a mismatch error shaping technique that shapes the errors outside a pass-band.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 3, 2018
    Assignee: NXP B.V.
    Inventors: Robert van Veldhoven, Rui Quan
  • Patent number: 10006972
    Abstract: A magnetic field sensor is disclosed for providing an output signal in response to an external magnetic field. The sensor comprises a primary magnetic field transducer for producing a primary signal in response to the external magnetic field and having a first magnetic field saturation characteristic; a secondary magnetic field transducer for producing a secondary signal in response to the external magnetic field and having a second magnetic field saturation characteristic. The first magnetic field saturation characteristic is different from the second magnetic field saturation characteristic. The sensor is configured to use the secondary signal to correct for errors in the output signal arising from saturation of the primary transducer.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: June 26, 2018
    Assignee: NXP B.V.
    Inventors: Klaus Reimann, Robert van Veldhoven, Jaap Ruigrok, Selcuk Ersoy, Ralf van Otten, Jörg Kock
  • Patent number: 9939496
    Abstract: A sensor system is disclosed. The sensor system includes a first sensor path comprising a first sensing element and a second sensing element being connected in series between a first supply terminal and a second supply terminal and an intermediate node connected in between the first supply terminal and the second supply terminal, a second sensor path comprising a third sensing element and a fourth sensing element connected in series between the first supply terminal and the second supply terminal, a first reference node connected in between the first supply terminal and the second supply terminal, and a second reference node connected in between the first supply terminal and the second supply terminal, and a processing unit to receive an input signal from the intermediate node, a first reference signal from the first reference node, and a second reference signal from the second reference node.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: April 10, 2018
    Assignee: NXP B.V.
    Inventors: Edwin Schapendonk, Pieter Van Der Zee, Fabio Sebastiano, Robert Van Veldhoven
  • Publication number: 20170154949
    Abstract: A diffused resistor and method for forming a diffused resistor are provided. The diffused resistor comprises a substrate having a first conductivity type; a first well within the substrate having a second conductivity type; and a second well within the first well having the first conductivity type. The resistor further comprises a first and second contact for coupling the resistor to further circuitry. The first and second contacts are each coupled to both the first well and the second well.
    Type: Application
    Filed: November 16, 2016
    Publication date: June 1, 2017
    Inventors: Robert van Veldhoven, Ibrahim Candan, Johannes van Geloven
  • Publication number: 20170139016
    Abstract: A magnetic field sensor is disclosed for providing an output signal in response to an external magnetic field. The sensor comprises a primary magnetic field transducer for producing a primary signal in response to the external magnetic field and having a first magnetic field saturation characteristic; a secondary magnetic field transducer for producing a secondary signal in response to the external magnetic field and having a second magnetic field saturation characteristic. The first magnetic field saturation characteristic is different from the second magnetic field saturation characteristic. The sensor is configured to use the secondary signal to correct for errors in the output signal arising from saturation of the primary transducer.
    Type: Application
    Filed: November 10, 2016
    Publication date: May 18, 2017
    Inventors: Klaus Reimann, Robert van Veldhoven, Jaap Ruigrok, Selcuk Ersoy, Ralf van Otten, Jörg Kock