Abstract: The various implementations described herein include systems, methods and/or devices used to enable secure erase in a memory device. In one aspect, the method includes detecting a secure erase trigger. The method further includes determining a secure erase algorithm from among one or more secure erase algorithms to use in accordance with the detected secure erase trigger. The method further includes performing a secure erase operation in accordance with the selected secure erase algorithm, the secure erase operation including: (1) signaling a secure erase condition to a plurality of controllers on the memory device, (2) erasing one or more non-volatile memory devices on the memory device, (3) monitoring the secure erase operation, and (4) recording data related to the secure erase operation.

Abstract: Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block.

Abstract: A circuit, configured to detect faults in an array of data storage elements, comprises: a resistor network; a switching network for selectively coupling a specified portion of the resistor network to the array of data storage elements; a current monitoring module, where the current monitoring module is operable to monitor current flow through the specified portion of the resistor network; and a control module coupled to the switching network and the current monitoring module. The control module is operable to control the switching network, so as to couple the specified portion of the resistor network to the array of data storage elements, and to determine whether one or more predefined characteristics of the output of the current monitoring module meet predetermined fault criteria. The control module is further operable to initiate one or more remedial actions, when the one or more predefined characteristics meet the predetermined fault criteria.

Abstract: A storage control system, and a method of operation thereof, including: a host interface module for receiving a host command from a host system; a power measurement module, coupled to the host interface module, for reading a current value of an electrical power supplied by the host system in response to the host command; and a schedule module, coupled to the power measurement module, for scheduling new operations to be executed in parallel in non-volatile memory devices, the new operations are scheduled when the current value of the electrical power does not exceed a power limit.

Abstract: Various embodiments described herein include systems, methods and/or devices used to dissipate heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board with one or more heat generating components coupled thereto. The electronic assembly further includes a second circuit board with one or more heat sensitive components coupled thereto. The electronic assembly also includes a thermal barrier interconnect. The thermal barrier interconnect electrically couples the first circuit board to the second circuit board. In some embodiments, thermal barrier interconnect is a flexible interconnect with a lower thermal conductivity than the first circuit board and the second circuit board. The thermal barrier interconnect forms a thermal barrier between the first and second circuit boards which protects the heat sensitive components from the heat generating components.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and a data hardening module in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is lower than an under-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is lower than the under-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device.

Abstract: An electronic system, and a method of manufacture thereof, including: a substrate; an electrical device over the substrate; and a surface mount heat sink next to the electrical device, the surface mount heat sink having an extruded shape characteristic of being formed using an extrusion mechanism.

Abstract: The various embodiments described herein include methods and/or devices used to protect data in a storage device. In one aspect, a method includes performing a power fail operation on a first section of the storage device, the first section of the storage device comprising one or more memory group modules. The power fail operation includes supplying power, via one or more energy storage devices, to the one or more memory group modules, where each memory group module includes a respective memory group module controller. The power fail operation also includes supplying power, via an additional energy storage device, to a storage device controller, the storage device controller corresponding to the first section of the storage device. The additional energy storage device is distinct from the one or more energy storage devices and each are distinct from a power source used during normal operation of the storage device.

Abstract: A storage control system and method of operation thereof includes: a control unit for initiating a hardening process beginning at a power-down signal; a counter module, coupled to the control unit for tracking a recorded time beginning at the power-down signal; a completion module, coupled to the counter module, for generating a work-complete entry in memory devices at a conclusion of the hardening process; and a calculation module, coupled to the completion module, for calculating a power down margin by determining the recorded time between the work-complete entry and a complete power loss of a hold-up power.

Abstract: The various embodiments described herein include circuits, methods and/or devices used to protect data in a storage device. In one aspect, a method includes performing a power fail operation on a first section of the storage device. The power fail operation includes supplying power, via an energy storage device, to the first section of the storage device, where the energy storage device is distinct from a power source used during normal operation of the storage device, and where supplying power via the energy storage device includes switching the output of the energy storage device from an output of a boost regulator to an input of the boost regulator. The power fail operation also includes performing data hardening on the first section of the storage device.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable power fail latching based on monitoring multiple power supply voltages in a storage device. In one aspect, the method includes: (1) determining whether a first power supply voltage provided to the storage device is out of range for a first time period, (2) determining whether a second power supply voltage provided to the storage device is out of range for a second time period, and (3) in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition.

Abstract: A storage device and method for performing a self-refresh operation are disclosed. In one embodiment, a storage device determines that the self-refresh operation needs to be performed. In response to that determination, the storage device performs the self-refresh operation by reading data from the memory and writing the data back to the memory without transferring the data outside of the storage device.

Abstract: The embodiments described herein include a method and device for adjusting trip points within a storage device. The method includes: obtaining one or more configuration parameters; and based on the one or more configuration parameters, determining a trip voltage. The method also includes comparing the trip voltage with an input voltage. The method further includes triggering a power fail condition in accordance with a determination that the input voltage is less than the trip voltage.

Abstract: The various implementations described herein include systems, methods and devices used to protect data in a storage device. In one aspect, a method includes, performing a soft power fail operation on a section of the device, the operation including: (1) signaling a power test condition to a first controller on the storage device; (2) providing one or more controllers with power from an energy storage device, where the energy storage device is distinct from a power supply used during normal operation; (3) signaling a power fail condition to the one or more controllers on the storage device, where the one or more controllers communicate with the first controller and correspond to said section of the storage device, and where, in response to the power fail condition, each of the one or more controllers performs a data hardening operation; and (4) resuming normal operation on said section of the storage device.

Abstract: A method of operation in a non-volatile memory system includes starting execution of a first memory operation from a first queue and in conjunction with starting a first timer, set to expire after a first predetermined time interval. The method further includes, in accordance with a determination that the first timer has expired, determining whether a second queue contains at least one memory operation for execution, and if so, suspending the first memory operation, executing a second memory operation from the second queue, and after completing execution of the second memory operation from the second queue, performing one or more subsequent operations (e.g., resuming execution of the first memory operation and restarting the first timer). In addition, the method includes, when the second queue does not contain at least one memory operation for execution, restarting the first timer, and continuing execution of the first memory operation from the first queue.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, a method includes, in response to a first signal received by the storage device, performing a soft power fail operation on a first section of the storage device. The soft power fail operation including: (1) signaling a power fail condition to a first plurality of controllers on the storage device, where the first plurality of controllers correspond to the first section of the storage device, (2) transferring data held in volatile memory of the storage device to non-volatile memory of the storage device, and (3) removing power from the first plurality of controllers.

Abstract: A storage control system, and a method of operation thereof, including: a host interface unit for receiving a host command from a host system; a power measurement hardware, coupled to the host interface unit, for reading a current value of electrical power supplied by the host system in response to the host command; and a power monitor controller, coupled to the power measurement hardware, for adjusting a bus speed for controlling data transfer through a channel shared by a number of non-volatile memory devices, the bus speed is adjusted based on the current value of the electrical power.

Abstract: The embodiments described herein are used to allocate memory in a storage system. The method includes, at a memory controller in the storage system, determining a current memory allocation for a set of memory devices, wherein the set of memory devices is formatted with a ratio of first storage density designated portions to second storage density designated portions in accordance with the current memory allocation. The method further includes detecting satisfaction of one or more memory reallocation trigger conditions. The method further includes, in response to detecting satisfaction of one or more memory reallocation trigger conditions, modifying the ratio of the first storage density designated portions to the second storage density designated portions in the set of memory devices to generate a second memory allocation for the set of memory devices.

Abstract: A method of operation of a storage control system includes: partitioning memory channels with memory devices; selecting a super device with one of the memory devices from one of the memory channels, the super device having a super chip select connected to chip selects of the memory devices; and selecting a super block associated with the super device.

Abstract: The various implementations described herein include systems, methods and/or devices used to transfer data within a storage device. In one aspect, a method includes reading data from a first non-volatile memory device to a shared bus, where the shared bus couples the first non-volatile memory device to a second non-volatile memory device and to the controller, and where the first non-volatile memory device is on a first die and the second non-volatile memory device is on a second die, distinct from the first die. The method further includes, in conjunction with reading the data from the first non-volatile memory device to the shared bus, generating a data strobe at the first non-volatile memory device; and, in response to receiving the data strobe at the second non-volatile memory device, transferring the data from the shared bus to the second non-volatile memory device.